S3D350A / S3D300A / S3D264A / S3D232A / S3D200A / S3K350A / S3K300A 32-bit RISC Microcontroller for Smart Card with optional AT1 Secure Libraries

CSV information

Status active
Valid from 01.02.2021
Valid until 01.02.2026
Scheme 🇫🇷 FR
Manufacturer SAMSUNG ELECTRONICS INC.
Category ICs, Smart Cards and Smart Card-Related Devices and Systems
Security level ASE_TSS.2, EAL6+
Protection profiles

Heuristics summary

Certificate ID: ANSSI-CC-2021/03

Certificate

Extracted keywords

Security level
EAL6, EAL2
Security Assurance Requirements (SAR)
ASE_TSS.2
Protection profiles
BSI-CC-PP-0084-2014
Certificates
ANSSI-CC-2021/03
Evaluation facilities
CEA-LETI

File metadata

Creation date D:20210208155826+01'00'
Modification date D:20210208155826+01'00'
Pages 2
Creator PScript5.dll Version 5.2.2
Producer Acrobat Distiller 11.0 (Windows)

Certification report

Extracted keywords

Symmetric Algorithms
AES, DES
Asymmetric Algorithms
ECC
Randomness
DTRNG
Libraries
AT1 Secure RSA/ECC/SHA Library v1.03, AT1 Secure RSA/ECC/SHA Library v2.01, AT1 Secure RSA/ECC/SHA Library v2.04, AT1 Secure RSA/ECC/SHA Library v2.05, AT1 Secure RSA/SHA Library v1.00

Vendor
Samsung

Security level
EAL 6, EAL2, EAL7, EAL 1, EAL 3, EAL 5, EAL 7, ITSEC E6 Elevé
Security Assurance Requirements (SAR)
ADV_ARC, ADV_FSP, ADV_IMP, ADV_INT, ADV_SPM, ADV_TDS, AGD_OPE, AGD_PRE, ALC_FLR, ALC_CMC, ALC_CMS, ALC_DEL, ALC_DVS, ALC_TAT, ATE_COV, ATE_DPT, ATE_FUN, ATE_IND, AVA_VAN, AVA_VAN.5, ASE_TSS.2, ASE_CCL, ASE_ECD, ASE_INT, ASE_OBJ, ASE_REQ, ASE_SPD, ASE_TSS
Protection profiles
BSI-CC-PP-0084-2014, BSI-PP-0084-2014
Certificates
ANSSI-CC-2021/03, ANSSI-CC-2019/59
Evaluation facilities
CESTI, CEA - LETI

Standards
AIS31, AIS 31, CCMB-2017-04-001, CCMB-2017-04-002, CCMB-2017-04-003, CCMB-2017-04-004

File metadata

Creation date D:20210208155613+01'00'
Modification date D:20210208155613+01'00'
Pages 16
Creator PScript5.dll Version 5.2.2
Producer Acrobat Distiller 11.0 (Windows)

References

Outgoing
  • ANSSI-CC-2019/59 - archived - S3D350A / S3D300A / S3D264A / S3D232A / S3D200A / S3K350A / S3K300A 32-bit RISC Microcontroller for Smart Card with optional AT1 Secure Libraries including specific IC Dedicated software

Security target

security target file processing did not finish successfully.
Download pdf: OK
Convert pdf to text: OK
Extract keywords: ERROR

Extracted keywords

Symmetric Algorithms
AES, DES, Triple-DES, TDES, TDEA, HMAC
Asymmetric Algorithms
RSA-CRT, ECDH, ECDSA, ECC, Diffie-Hellman, DSA
Hash functions
SHA1, SHA-1, SHA224, SHA256, SHA384, SHA512, SHA-224, SHA-256, SHA-384, SHA-512
Schemes
Key Agreement
Randomness
DTRNG, TRNG, RNG, RND
Libraries
AT1 Secure RSA/ECC/SHA Library v1.00, AT1 Secure RSA/ECC/SHA Library v1.03, AT1 Secure RSA/ECC/SHA Library v2.01, AT1 Secure RSA/ECC/SHA Library v2.04, AT1 Secure RSA/ECC/SHA library
Elliptic Curves
P-192, P-224, P-256, P-384, secp192k1, secp192r1, secp224k1, secp224r1, secp256k1, secp256r1, secp384r1, brainpoolP192r1, brainpoolP192t1, brainpoolP224r1, brainpoolP224t1, brainpoolP256r1, brainpoolP256t1, brainpoolP320r1, brainpoolP320t1, brainpoolP384r1, brainpoolP384t1, brainpoolP512r1, brainpoolP512t1
Block cipher modes
ECB

CPLC
IC Version
Vendor
Samsung

Security level
EAL6+, EAL6, EAL 4, EAL 6, EAL6 augmented, EAL 4 augmented, EAL 6 augmented
Claims
O.RSA, O.ECC, O.RND, O.SHA, O.TDES, O.AES, O.ECDSA, O.ECDH, O.MEM_ACCESS, T.RND
Security Assurance Requirements (SAR)
ADV_ARC, ADV_FSP, ADV_IMP, ADV_ARC.1, ADV_FSP.5, ADV_IMP.2, ADV_INT.3, ADV_TDS.5, ADV_SPM.1, ADV_FSP.4, AGD_OPE, AGD_PRE, AGD_OPE.1, AGD_PRE.1, ALC_DVS.2, ALC_DEL, ALC_DVS, ALC_CMS, ALC_CMC, ALC_CMC.5, ALC_CMS.5, ALC_DEL.1, ALC_LCD.1, ALC_TAT.3, ALC_CMS.4, ATE_COV, ATE_COV.3, ATE_DPT.3, ATE_FUN.2, ATE_IND.2, AVA_VAN.5, AVA_VAN, APE_ECD, ASE_TSS.2, ASE_CCL.1, ASE_ECD.1, ASE_INT.1, ASE_OBJ.2, ASE_REQ.2, ASE_SPD.1, ASE_REQ.1
Security Functional Requirements (SFR)
FAU_SAS, FAU_GEN, FAU_SAS.1, FAU_SAS.1.1, FAU_GEN.1, FCS_RNG, FCS_RNG.1, FCS_RNG.1.1, FCS_RNG.1.2, FCS_COP.1, FCS_COP, FCS_CKM.1, FCS_CKM.4, FCS_CKM, FCS_CKM.2, FDP_SDC, FDP_ACF, FDP_SDC.1, FDP_SDI, FDP_SDC.1.1, FDP_SDI.2, FDP_SDI.1, FDP_SDI.2.1, FDP_SDI.2.2, FDP_ITT.1, FDP_ITT.1.1, FDP_ACC.1, FDP_IFC.1, FDP_IFC.1.1, FDP_IFF.1, FDP_ACF.1, FDP_ACC.1.1, FDP_ACF.1.1, FDP_ACF.1.2, FDP_ACF.1.3, FDP_ACF.1.4, FDP_ITC.1, FDP_ITC.2, FDP_UCT.1, FDP_UCT.1.1, FDP_UIT.1, FDP_UIT.1.1, FDP_UIT.1.2, FDP_ACC, FDP_IFC, FDP_ITT, FIA_API, FIA_API.1, FIA_API.1.1, FMT_LIM, FMT_LIM.1, FMT_LIM.2, FMT_LIM.1.1, FMT_LIM.2.1, FMT_MSA.3, FMT_MSA.1, FMT_MSA.3.1, FMT_MSA.3.2, FMT_SMR.1, FMT_MSA.1.1, FMT_SMF.1, FMT_SMF.1.1, FMT_CKM.4, FMT_MSA, FMT_SMF, FPT_FLS.1, FPT_FLS.1.1, FPT_PHP.3, FPT_PHP.3.1, FPT_PHP, FPT_ITT.1, FPT_ITT.1.1, FPT_FLS, FPT_ITT, FRU_FLT.2, FRU_FLT.1, FRU_FLT.2.1, FRU_FLT, FTP_ITC.1, FTP_ITC.1.1, FTP_ITC.1.2, FTP_ITC.1.3, FTP_TRP.1
Protection profiles
BSI-CC-PP-0084, BSI-PP-0084, BSI-CC-PP-0084-

Side-channel analysis
Leak-Inherent, Physical Probing, physical probing, Physical probing, side-channel, side channel, DPA, SPA, timing attacks, timing attack, physical tampering, Malfunction, malfunction, DFA, reverse engineering

Standards
FIPS PUB 180-3, FIPS197, FIPS 197, BSI-AIS31, AIS31, ISO/IEC 18032, CCMB-2017-04-001, CCMB-2017-04-002, CCMB-2017-04-003, CCMB-2017-04-004

Heuristics

Automated inference - use with caution

All attributes shown in this section (e.g., links between certificates, products, vendors, and known CVEs) are generated by automated heuristics and have not been reviewed by humans. These methods can produce false positives or false negatives and should not be treated as definitive without independent verification. For details on our data sources and inference methods, see our methodology. If you believe any information here is inaccurate or harmful, please submit feedback.

Certificate ID

ANSSI-CC-2021/03

Extracted SARs

ADV_ARC.1, ADV_FSP.5, ADV_IMP.2, ADV_INT.3, ADV_SPM.1, ADV_TDS.5, AGD_OPE.1, AGD_PRE.1, ALC_CMC.5, ALC_CMS.5, ALC_DEL.1, ALC_DVS.2, ALC_LCD.1, ALC_TAT.3, ASE_CCL.1, ASE_ECD.1, ASE_INT.1, ASE_OBJ.2, ASE_REQ.2, ASE_SPD.1, ASE_TSS.2, ATE_COV.3, ATE_DPT.3, ATE_FUN.2, ATE_IND.2, AVA_VAN.5

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Showing 5 out of 58.

References

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Raw data

{
  "_type": "sec_certs.sample.cc.CCCertificate",
  "category": "ICs, Smart Cards and Smart Card-Related Devices and Systems",
  "cert_link": "https://www.commoncriteriaportal.org/nfs/ccpfiles/files/epfiles/certificat-2021_03.pdf",
  "dgst": "2d388891789e3090",
  "heuristics": {
    "_type": "sec_certs.sample.cc.CCCertificate.Heuristics",
    "annotated_references": null,
    "cert_id": "ANSSI-CC-2021/03",
    "cert_lab": null,
    "cpe_matches": null,
    "direct_transitive_cves": null,
    "eal": "EAL6+",
    "extracted_sars": {
      "_type": "Set",
      "elements": [
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ADV_TDS",
          "level": 5
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ALC_DEL",
          "level": 1
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ATE_FUN",
          "level": 2
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ALC_CMS",
          "level": 5
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ATE_DPT",
          "level": 3
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ADV_ARC",
          "level": 1
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ASE_CCL",
          "level": 1
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ASE_ECD",
          "level": 1
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ALC_DVS",
          "level": 2
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ASE_TSS",
          "level": 2
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ALC_TAT",
          "level": 3
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "AVA_VAN",
          "level": 5
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ATE_IND",
          "level": 2
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ASE_INT",
          "level": 1
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ALC_LCD",
          "level": 1
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ADV_INT",
          "level": 3
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "AGD_OPE",
          "level": 1
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "AGD_PRE",
          "level": 1
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ALC_CMC",
          "level": 5
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ASE_REQ",
          "level": 2
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ASE_SPD",
          "level": 1
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ADV_FSP",
          "level": 5
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ATE_COV",
          "level": 3
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ADV_SPM",
          "level": 1
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ADV_IMP",
          "level": 2
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ASE_OBJ",
          "level": 2
        }
      ]
    },
    "extracted_versions": {
      "_type": "Set",
      "elements": [
        "32"
      ]
    },
    "indirect_transitive_cves": null,
    "next_certificates": null,
    "prev_certificates": null,
    "protection_profiles": {
      "_type": "Set",
      "elements": [
        "cf0f01bcd7be3e9c"
      ]
    },
    "related_cves": null,
    "report_references": {
      "_type": "sec_certs.sample.certificate.References",
      "directly_referenced_by": null,
      "directly_referencing": {
        "_type": "Set",
        "elements": [
          "ANSSI-CC-2019/59"
        ]
      },
      "indirectly_referenced_by": null,
      "indirectly_referencing": {
        "_type": "Set",
        "elements": [
          "ANSSI-CC-2019/59",
          "ANSSI-CC-2017/11",
          "ANSSI-CC-2018/12",
          "ANSSI-CC-2019/01",
          "ANSSI-CC-2017/53"
        ]
      }
    },
    "scheme_data": null,
    "st_references": {
      "_type": "sec_certs.sample.certificate.References",
      "directly_referenced_by": null,
      "directly_referencing": null,
      "indirectly_referenced_by": null,
      "indirectly_referencing": null
    },
    "verified_cpe_matches": null
  },
  "maintenance_updates": {
    "_type": "Set",
    "elements": []
  },
  "manufacturer": "SAMSUNG ELECTRONICS INC.",
  "manufacturer_web": "https://www.samsung.com/sec",
  "name": "S3D350A / S3D300A / S3D264A / S3D232A / S3D200A / S3K350A / S3K300A 32-bit RISC Microcontroller for Smart Card with optional AT1 Secure Libraries",
  "not_valid_after": "2026-02-01",
  "not_valid_before": "2021-02-01",
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