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S3FV9QM/S3FV9QK 32-bit RISC Microcontroller for Smart Card with optional Secure RSA/ECC/SHA Library
Certificate details
| Status | archived |
|---|---|
| Valid from | 05.11.2018 |
| Valid until | 05.11.2023 |
| Scheme | 🇫🇷 FR |
| Manufacturer | Samsung Electronics Co., Ltd. |
| Category | Trusted Computing |
| Security level | EAL5+, ALC_DVS.2, AVA_VAN.5 |
| Protection profiles |
Certificate
certificate could not be downloaded, no link is available.
Certification report
Extracted keywords
Symmetric Algorithms
AES, DES, Triple-DESAsymmetric Algorithms
ECCRandomness
DTRNGVendor
SamsungSecurity level
EAL 5, EAL2, EAL7, EAL 1, EAL 3, EAL 7, ITSEC E6 ElevéSecurity Assurance Requirements (SAR)
ADV_ARC, ADV_FSP, ADV_IMP, ADV_INT, ADV_SPM, ADV_TDS, AGD_OPE, AGD_PRE, ALC_DVS.2, ALC_FLR, ALC_CMC, ALC_CMS, ALC_DEL, ALC_DVS, ALC_LCD, ALC_TAT, ATE_COV, ATE_DPT, ATE_FUN, ATE_IND, AVA_VAN.5, AVA_VAN, ASE_CCL, ASE_ECD, ASE_INT, ASE_OBJ, ASE_REQ, ASE_SPD, ASE_TSSProtection profiles
BSI-CC-PP-0035-2007, BSI-PP-0035-2007Certificates
ANSSI-CC-2018/43, ANSSI-CC-2017/16Evaluation facilities
CESTI, CEA - LETI, CEA-LETIStandards
AIS 31, CCMB-2017-04-001, CCMB-2017-04-002, CCMB-2017-04-003, CCMB-2017-04-004Frontpage
| Certified item | ### Samsung S3FV9QM/S3FV9QK 32-bit RISC Microcontroller for Smart Card with optional Secure RSA/ECC/SHA Library including specific IC Dedicated Software Référence/version du produit |
|---|---|
| Certification lab | ## ANSSI-CC-2018/43 revision 3 ### EAL 5 augmenté ALC_DVS.2, AVA_VAN.5 ### Samsung Electronics Co Ltd. 17 Floor, B-Tower, 1-1, Samsungjeonja-ro Hwaseong-si, Gyeonggi-do 445-330, Corée du Sud ### Samsung Electronics Co Ltd. 17 Floor, B-Tower, 1-1, Samsungjeonja-ro Hwaseong-si, Gyeonggi-do 445-330, Corée du Sud ## CEA - LETI 17 avenue des martyrs, 38054 Grenoble Cedex 9, France |
| Developer | Commanditaire |
Cross-references
Outgoing- ANSSI-CC-2017/16 - archived - SAMSUNG S3FV9QM / S3FV9QK référence : S3FV9QM/S3FV9QK rev3_TRCv1.0_PKALibv1.4-GUIv1.38a_DTRNGlibv2.0/3.0-Iv1.2_BLv2.1/2.2-GUI1.2_BLv2.6-GUIv1.2.7_DOC-UMv1.11-SANv1.5-CDSv3.2
- ANSSI-CC-2021/02 - archived - Samsung S3FV9QM/S3FV9QK 32-bit RISC Microcontroller for Smart Card with optional Secure RSA/ECC/SHA Libraries including specific IC Dedicated Software Référence : S3FV9QM_20200504
Security target
Extracted keywords
Symmetric Algorithms
AES, DES, TDES, 3DES, Triple-DES, TDEA, HMACAsymmetric Algorithms
RSA-CRT, ECDH, ECDSA, ECC, Diffie-Hellman, DSAHash functions
SHA1, SHA224, SHA256, SHA384, SHA512Schemes
Key AgreementProtocols
PGPRandomness
DTRNG, TRNG, RND, RNGElliptic Curves
P-192, P-224, P-256, P-384, P-521, secp192k1, secp192r1, secp224k1, secp224r1, secp256k1, secp256r1, secp384r1, secp521r1, brainpoolP192r1, brainpoolP192t1, brainpoolP224r1, brainpoolP224t1, brainpoolP256r1, brainpoolP256t1, brainpoolP320r1, brainpoolP320t1, brainpoolP384r1, brainpoolP384t1, brainpoolP512r1, brainpoolP512t1Block cipher modes
ECBCPLC
IC VersionVendor
SamsungSecurity level
EAL5, EAL 4, EAL5+, EAL 5, EAL5 augmented, EAL 4 augmented, EAL 5 augmentedClaims
O.RNG, O.RND, O.MEM_ACCESS, T.RNDSecurity Assurance Requirements (SAR)
ADV_ARV, ADV_FSP, ADV_IMP, ADV_VAN, ADV_ARC.1, ADV_FSP.5, ADV_IMP.1, ADV_INT.2, ADV_TDS.4, ADV_FSP.4, ADV_TDS.3, AGD_OPE, AGD_PRE, AGD_OPE.1, AGD_PRE.1, ALC_DVS.2, ALC_DEL, ALC_DVS, ALC_CMS, ALC_CMC, ALC_CMC.4, ALC_CMS.5, ALC_DEL.1, ALC_LCD.1, ALC_TAT.2, ALC_DVS.1, ALC_CMS.4, ATE_COV, ATE_COV.2, ATE_DPT.3, ATE_FUN.1, ATE_IND.2, ATE_DPT.1, AVA_VAN.5, ASE_CCL.1, ASE_ECD.1, ASE_INT.1, ASE_OBJ.2, ASE_REQ.2, ASE_SPD.1, ASE_TSS.1Security Functional Requirements (SFR)
FAU_SAS, FAU_GEN, FAU_SAS.1, FAU_SAS.1.1, FAU_GEN.1, FCS_RNG, FCS_RNG.1, FCS_RNG.1.1, FCS_RNG.1.2, FCS_COP.1, FCS_COP, FCS_CKM.1, FCS_CKM.4, FCS_CKM, FCS_CKM.2, FDP_ACF, FDP_ITT.1, FDP_ITT.1.1, FDP_ACC.1, FDP_IFC.1, FDP_IFC.1.1, FDP_IFF.1, FDP_ACF.1, FDP_ACC.1.1, FDP_ACF.1.1, FDP_ACF.1.2, FDP_ACF.1.3, FDP_ACF.1.4, FDP_ITC.1, FDP_ITC.2, FDP_SDI.1, FDP_ACC, FDP_IFC, FDP_ITT, FMT_LIM, FMT_LIM.1, FMT_LIM.2, FMT_LIM.1.1, FMT_LIM.2.1, FMT_MSA.3, FMT_MSA.1, FMT_MSA.3.1, FMT_MSA.3.2, FMT_SMR.1, FMT_MSA.1.1, FMT_SMF.1, FMT_SMF.1.1, FMT_CKM.4, FMT_MSA, FMT_SMF, FPT_FLS.1, FPT_FLS.1.1, FPT_PHP.3, FPT_PHP.3.1, FPT_PHP, FPT_ITT.1, FPT_ITT.1.1, FPT_FLS, FPT_ITT, FRU_FLT.2, FRU_FLT.1, FRU_FLT.2.1, FRU_FLTProtection profiles
BSI-PP-0035Side-channel analysis
Leak-Inherent, Physical Probing, physical probing, Physical probing, side-channel, side channel, DPA, SPA, timing attacks, timing attack, physical tampering, Malfunction, malfunction, DFA, reverse engineeringStandards
FIPS PUB 180-3, FIPS 197, BSI-AIS31, AIS31, AIS 31, CCMB-2017-04-001, CCMB-2017-04-004, CCMB-2017-04-002, CCMB-2017-04-003Automated analysis
Automated inference - use with caution
All attributes shown in this section (e.g., links between certificates, products, vendors, and known CVEs) are generated by automated heuristics and have not been reviewed by humans. These methods can produce false positives or false negatives and should not be treated as definitive without independent verification. This applies equally to the Cross-references section below. If you want to know more about how this data is computed and how reliable it is, see our documentation on automated analysis. If you believe any information here is inaccurate or harmful, please submit feedback.Certificate ID
ANSSI-CC-2018/43Extracted SARs
ADV_ARC.1, ADV_FSP.5, ADV_IMP.1, ADV_INT.2, ADV_TDS.4, AGD_OPE.1, AGD_PRE.1, ALC_CMC.4, ALC_CMS.5, ALC_DEL.1, ALC_DVS.2, ALC_LCD.1, ALC_TAT.2, ASE_CCL.1, ASE_ECD.1, ASE_INT.1, ASE_OBJ.2, ASE_REQ.2, ASE_SPD.1, ASE_TSS.1, ATE_COV.2, ATE_DPT.3, ATE_FUN.1, ATE_IND.2, AVA_VAN.5Similar certificates
Showing 5 out of 59.
Cross-references
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The certificate was first processed.
{
"_type": "sec_certs.sample.cc.CCCertificate",
"category": "Trusted Computing",
"cert_link": null,
"dgst": "49fdbc726cff0629",
"heuristics": {
"_type": "sec_certs.sample.cc_eucc_common.Heuristics",
"annotated_references": null,
"cert_id": "ANSSI-CC-2018/43",
"cert_lab": [
"##"
],
"cpe_matches": null,
"direct_transitive_cves": null,
"eal": "EAL5+",
"extracted_sars": {
"_type": "Set",
"elements": [
{
"_type": "sec_certs.sample.sar.SAR",
"family": "ALC_DVS",
"level": 2
},
{
"_type": "sec_certs.sample.sar.SAR",
"family": "ADV_INT",
"level": 2
},
{
"_type": "sec_certs.sample.sar.SAR",
"family": "ATE_COV",
"level": 2
},
{
"_type": "sec_certs.sample.sar.SAR",
"family": "ALC_CMS",
"level": 5
},
{
"_type": "sec_certs.sample.sar.SAR",
"family": "ASE_OBJ",
"level": 2
},
{
"_type": "sec_certs.sample.sar.SAR",
"family": "ASE_INT",
"level": 1
},
{
"_type": "sec_certs.sample.sar.SAR",
"family": "ALC_TAT",
"level": 2
},
{
"_type": "sec_certs.sample.sar.SAR",
"family": "ALC_CMC",
"level": 4
},
{
"_type": "sec_certs.sample.sar.SAR",
"family": "ASE_TSS",
"level": 1
},
{
"_type": "sec_certs.sample.sar.SAR",
"family": "ALC_LCD",
"level": 1
},
{
"_type": "sec_certs.sample.sar.SAR",
"family": "ATE_IND",
"level": 2
},
{
"_type": "sec_certs.sample.sar.SAR",
"family": "ALC_DEL",
"level": 1
},
{
"_type": "sec_certs.sample.sar.SAR",
"family": "ADV_ARC",
"level": 1
},
{
"_type": "sec_certs.sample.sar.SAR",
"family": "AGD_PRE",
"level": 1
},
{
"_type": "sec_certs.sample.sar.SAR",
"family": "ASE_SPD",
"level": 1
},
{
"_type": "sec_certs.sample.sar.SAR",
"family": "AGD_OPE",
"level": 1
},
{
"_type": "sec_certs.sample.sar.SAR",
"family": "ADV_TDS",
"level": 4
},
{
"_type": "sec_certs.sample.sar.SAR",
"family": "ATE_DPT",
"level": 3
},
{
"_type": "sec_certs.sample.sar.SAR",
"family": "ASE_CCL",
"level": 1
},
{
"_type": "sec_certs.sample.sar.SAR",
"family": "ATE_FUN",
"level": 1
},
{
"_type": "sec_certs.sample.sar.SAR",
"family": "ADV_IMP",
"level": 1
},
{
"_type": "sec_certs.sample.sar.SAR",
"family": "ADV_FSP",
"level": 5
},
{
"_type": "sec_certs.sample.sar.SAR",
"family": "ASE_ECD",
"level": 1
},
{
"_type": "sec_certs.sample.sar.SAR",
"family": "AVA_VAN",
"level": 5
},
{
"_type": "sec_certs.sample.sar.SAR",
"family": "ASE_REQ",
"level": 2
}
]
},
"extracted_versions": {
"_type": "Set",
"elements": [
"32"
]
},
"indirect_transitive_cves": null,
"next_certificates": null,
"prev_certificates": null,
"protection_profiles": {
"_type": "Set",
"elements": [
"f6d23054061d72ba"
]
},
"related_cves": null,
"report_references": {
"_type": "sec_certs.sample.certificate.References",
"directly_referenced_by": {
"_type": "Set",
"elements": [
"ANSSI-CC-2021/02"
]
},
"directly_referencing": {
"_type": "Set",
"elements": [
"ANSSI-CC-2017/16"
]
},
"indirectly_referenced_by": {
"_type": "Set",
"elements": [
"ANSSI-CC-2021/02",
"ANSSI-CC-2021/02-R01",
"ANSSI-CC-2021/02-R02"
]
},
"indirectly_referencing": {
"_type": "Set",
"elements": [
"ANSSI-CC-2014/22",
"ANSSI-CC-2014/75",
"ANSSI-CC-2017/16"
]
}
},
"scheme_data": null,
"st_references": {
"_type": "sec_certs.sample.certificate.References",
"directly_referenced_by": null,
"directly_referencing": null,
"indirectly_referenced_by": null,
"indirectly_referencing": null
},
"verified_cpe_matches": null
},
"maintenance_updates": {
"_type": "Set",
"elements": []
},
"manufacturer": "Samsung Electronics Co., Ltd.",
"manufacturer_web": "https://www.samsung.com",
"name": "S3FV9QM/S3FV9QK 32-bit RISC Microcontroller for Smart Card with optional Secure RSA/ECC/SHA Library",
"not_valid_after": "2023-11-05",
"not_valid_before": "2018-11-05",
"pdf_data": {
"_type": "sec_certs.sample.cc_eucc_common.PdfData",
"cert_filename": null,
"cert_frontpage": null,
"cert_keywords": null,
"cert_metadata": null,
"report_filename": "anssi-cc-2018-43fr.pdf",
"report_frontpage": {
"FR": {
"cc_security_level": "",
"cc_version": "### Crit\u00e8res Communs version 3.1 r\u00e9vision 5",
"cert_id": "",
"cert_item": "### Samsung S3FV9QM/S3FV9QK 32-bit RISC Microcontroller for Smart Card with optional Secure RSA/ECC/SHA Library including specific IC Dedicated Software R\u00e9f\u00e9rence/version du produit",
"cert_item_version": "",
"cert_lab": "## ANSSI-CC-2018/43 revision 3 ### EAL 5 augment\u00e9 ALC_DVS.2, AVA_VAN.5 ### Samsung Electronics Co Ltd. 17 Floor, B-Tower, 1-1, Samsungjeonja-ro Hwaseong-si, Gyeonggi-do 445-330, Cor\u00e9e du Sud ### Samsung Electronics Co Ltd. 17 Floor, B-Tower, 1-1, Samsungjeonja-ro Hwaseong-si, Gyeonggi-do 445-330, Cor\u00e9e du Sud ## CEA - LETI 17 avenue des martyrs, 38054 Grenoble Cedex 9, France",
"developer": "Commanditaire",
"match_rules": [
"R\u00e9f\u00e9rence du rapport de certification(.+)Nom du produit(.+)()Conformit\u00e9 \u00e0 un profil de protection(.+)Crit\u00e8res d\u0027\u00e9valuation et version(.+)Niveau d\u0027\u00e9valuation(.+)D\u00e9veloppeur (.+)Centre d\u0027\u00e9valuation(.+)Accords de reconnaissance applicables"
],
"ref_protection_profiles": "### Security IC Platform Protection Profile, version 1.0, certifi\u00e9 BSI-CC-PP-0035-2007 le 23 ao\u00fbt 2007"
}
},
"report_keywords": {
"asymmetric_crypto": {
"ECC": {
"ECC": {
"ECC": 1
}
}
},
"cc_cert_id": {
"FR": {
"ANSSI-CC-2017/16": 1,
"ANSSI-CC-2018/43": 18
}
},
"cc_claims": {},
"cc_protection_profile_id": {
"BSI": {
"BSI-CC-PP-0035-2007": 1,
"BSI-PP-0035-2007": 1
}
},
"cc_sar": {
"ADV": {
"ADV_ARC": 1,
"ADV_FSP": 1,
"ADV_IMP": 1,
"ADV_INT": 1,
"ADV_SPM": 1,
"ADV_TDS": 1
},
"AGD": {
"AGD_OPE": 1,
"AGD_PRE": 1
},
"ALC": {
"ALC_CMC": 2,
"ALC_CMS": 1,
"ALC_DEL": 1,
"ALC_DVS": 1,
"ALC_DVS.2": 2,
"ALC_FLR": 2,
"ALC_LCD": 1,
"ALC_TAT": 1
},
"ASE": {
"ASE_CCL": 1,
"ASE_ECD": 1,
"ASE_INT": 1,
"ASE_OBJ": 1,
"ASE_REQ": 1,
"ASE_SPD": 1,
"ASE_TSS": 1
},
"ATE": {
"ATE_COV": 1,
"ATE_DPT": 1,
"ATE_FUN": 1,
"ATE_IND": 1
},
"AVA": {
"AVA_VAN": 2,
"AVA_VAN.5": 3
}
},
"cc_security_level": {
"EAL": {
"EAL 1": 1,
"EAL 3": 1,
"EAL 5": 3,
"EAL 7": 1,
"EAL2": 2,
"EAL7": 1
},
"ITSEC": {
"ITSEC E6 Elev\u00e9": 1
}
},
"cc_sfr": {},
"certification_process": {},
"cipher_mode": {},
"cplc_data": {},
"crypto_engine": {},
"crypto_library": {},
"crypto_protocol": {},
"crypto_scheme": {},
"device_model": {},
"ecc_curve": {},
"eval_facility": {
"CEA-LETI": {
"CEA - LETI": 1,
"CEA-LETI": 1
},
"CESTI": {
"CESTI": 3
}
},
"hash_function": {},
"ic_data_group": {},
"javacard_api_const": {},
"javacard_packages": {},
"javacard_version": {},
"os_name": {},
"pq_crypto": {},
"randomness": {
"TRNG": {
"DTRNG": 7
}
},
"side_channel_analysis": {},
"standard_id": {
"BSI": {
"AIS 31": 2
},
"CC": {
"CCMB-2017-04-001": 1,
"CCMB-2017-04-002": 1,
"CCMB-2017-04-003": 1,
"CCMB-2017-04-004": 1
}
},
"symmetric_crypto": {
"AES_competition": {
"AES": {
"AES": 1
}
},
"DES": {
"3DES": {
"Triple-DES": 1
},
"DES": {
"DES": 1
}
}
},
"technical_report_id": {},
"tee_name": {},
"tls_cipher_suite": {},
"vendor": {
"Samsung": {
"Samsung": 27
}
},
"vulnerability": {}
},
"report_metadata": {
"/Category": "revision 3",
"/Comments": "Samsung Electronics Co Ltd.",
"/Company": "SGDSN/ANSSI",
"/CreationDate": "D:20181120145904+01\u002700\u0027",
"/Creator": "Acrobat PDFMaker 11 pour Word",
"/Keywords": "ANSSI-CC-CER-F-07.026",
"/ModDate": "D:20181127163721+01\u002700\u0027",
"/Producer": "Adobe PDF Library 11.0",
"/SourceModified": "D:20181120135900",
"/Subject": "Samsung S3FV9QM/S3FV9QK 32-bit RISC Microcontroller for Smart Card with optional Secure RSA/ECC/SHA Library including specific IC Dedicated Software",
"/Title": "ANSSI-CC-2018/43",
"pdf_file_size_bytes": 336598,
"pdf_hyperlinks": {
"_type": "Set",
"elements": [
"http://www.ssi.gouv.fr/",
"mailto:[email protected]"
]
},
"pdf_is_encrypted": false,
"pdf_number_of_pages": 18
},
"st_filename": "anssi-cible-2018_43en.pdf",
"st_frontpage": null,
"st_keywords": {
"asymmetric_crypto": {
"ECC": {
"ECC": {
"ECC": 23
},
"ECDH": {
"ECDH": 6
},
"ECDSA": {
"ECDSA": 12
}
},
"FF": {
"DH": {
"Diffie-Hellman": 2
},
"DSA": {
"DSA": 2
}
},
"RSA": {
"RSA-CRT": 1
}
},
"cc_cert_id": {},
"cc_claims": {
"O": {
"O.MEM_ACCESS": 1,
"O.RND": 5,
"O.RNG": 1
},
"T": {
"T.RND": 4
}
},
"cc_protection_profile_id": {
"BSI": {
"BSI-PP-0035": 5
}
},
"cc_sar": {
"ADV": {
"ADV_ARC.1": 7,
"ADV_ARV": 1,
"ADV_FSP": 2,
"ADV_FSP.4": 2,
"ADV_FSP.5": 3,
"ADV_IMP": 1,
"ADV_IMP.1": 2,
"ADV_INT.2": 1,
"ADV_TDS.3": 1,
"ADV_TDS.4": 1,
"ADV_VAN": 1
},
"AGD": {
"AGD_OPE": 1,
"AGD_OPE.1": 2,
"AGD_PRE": 1,
"AGD_PRE.1": 2
},
"ALC": {
"ALC_CMC": 1,
"ALC_CMC.4": 1,
"ALC_CMS": 2,
"ALC_CMS.4": 1,
"ALC_CMS.5": 3,
"ALC_DEL": 1,
"ALC_DEL.1": 1,
"ALC_DVS": 1,
"ALC_DVS.1": 1,
"ALC_DVS.2": 7,
"ALC_LCD.1": 1,
"ALC_TAT.2": 1
},
"ASE": {
"ASE_CCL.1": 1,
"ASE_ECD.1": 1,
"ASE_INT.1": 1,
"ASE_OBJ.2": 1,
"ASE_REQ.2": 1,
"ASE_SPD.1": 1,
"ASE_TSS.1": 1
},
"ATE": {
"ATE_COV": 1,
"ATE_COV.2": 1,
"ATE_DPT.1": 1,
"ATE_DPT.3": 1,
"ATE_FUN.1": 1,
"ATE_IND.2": 1
},
"AVA": {
"AVA_VAN.5": 13
}
},
"cc_security_level": {
"EAL": {
"EAL 4": 1,
"EAL 4 augmented": 1,
"EAL 5": 2,
"EAL 5 augmented": 2,
"EAL5": 6,
"EAL5 augmented": 1,
"EAL5+": 1
}
},
"cc_sfr": {
"FAU": {
"FAU_GEN": 2,
"FAU_GEN.1": 1,
"FAU_SAS": 8,
"FAU_SAS.1": 12,
"FAU_SAS.1.1": 2
},
"FCS": {
"FCS_CKM": 9,
"FCS_CKM.1": 30,
"FCS_CKM.2": 4,
"FCS_CKM.4": 14,
"FCS_COP": 33,
"FCS_COP.1": 32,
"FCS_RNG": 6,
"FCS_RNG.1": 15,
"FCS_RNG.1.1": 2,
"FCS_RNG.1.2": 2
},
"FDP": {
"FDP_ACC": 1,
"FDP_ACC.1": 14,
"FDP_ACC.1.1": 1,
"FDP_ACF": 2,
"FDP_ACF.1": 10,
"FDP_ACF.1.1": 1,
"FDP_ACF.1.2": 1,
"FDP_ACF.1.3": 1,
"FDP_ACF.1.4": 1,
"FDP_IFC": 1,
"FDP_IFC.1": 18,
"FDP_IFC.1.1": 1,
"FDP_IFF.1": 3,
"FDP_ITC.1": 11,
"FDP_ITC.2": 11,
"FDP_ITT": 1,
"FDP_ITT.1": 17,
"FDP_ITT.1.1": 1,
"FDP_SDI.1": 1
},
"FMT": {
"FMT_CKM.4": 1,
"FMT_LIM": 8,
"FMT_LIM.1": 24,
"FMT_LIM.1.1": 2,
"FMT_LIM.2": 28,
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