S3FV9QM/S3FV9QK 32-bit RISC Microcontroller for Smart Card with optional Secure RSA/ECC/SHA Library

CSV information

Status archived
Valid from 05.11.2018
Valid until 05.11.2023
Scheme 🇫🇷 FR
Manufacturer Samsung Electronics Co., Ltd.
Category Trusted Computing
Security level ALC_DVS.2, EAL5+, AVA_VAN.5
Protection profiles

Heuristics summary

Certificate ID: ANSSI-CC-2018/43

Certificate

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Certification report

Extracted keywords

Symmetric Algorithms
AES, DES, Triple-DES
Asymmetric Algorithms
ECC
Randomness
DTRNG

Vendor
Samsung

Security level
EAL 5, EAL2, EAL7, EAL 1, EAL 3, EAL 7, ITSEC E6 Elevé
Security Assurance Requirements (SAR)
ADV_ARC, ADV_FSP, ADV_IMP, ADV_INT, ADV_SPM, ADV_TDS, AGD_OPE, AGD_PRE, ALC_DVS.2, ALC_FLR, ALC_CMC, ALC_CMS, ALC_DEL, ALC_DVS, ALC_TAT, ATE_COV, ATE_DPT, ATE_FUN, ATE_IND, AVA_VAN.5, AVA_VAN, ASE_CCL, ASE_ECD, ASE_INT, ASE_OBJ, ASE_REQ, ASE_SPD, ASE_TSS
Protection profiles
BSI-CC-PP-0035-2007, BSI-PP-0035-2007
Certificates
ANSSI-CC-2018/43, ANSSI-CC-2017/16
Evaluation facilities
CESTI, CEA - LETI, CEA-LETI

Standards
AIS 31, CCMB-2017-04-001, CCMB-2017-04-002, CCMB-2017-04-003, CCMB-2017-04-004

File metadata

Title ANSSI-CC-2018/43
Subject Samsung S3FV9QM/S3FV9QK 32-bit RISC Microcontroller for Smart Card with optional Secure RSA/ECC/SHA Library including specific IC Dedicated Software
Keywords ANSSI-CC-CER-F-07.026
Creation date D:20181120145904+01'00'
Modification date D:20181127163721+01'00'
Pages 18
Creator Acrobat PDFMaker 11 pour Word
Producer Adobe PDF Library 11.0

Frontpage

Certificate ID ANSSI-CC-2018/43
Certified item Samsung S3FV9QM/S3FV9QK 32-bit RISC Microcontroller for Smart Card with optional Secure RSA/ECC/SHA Library including specific IC Dedicated Software
Certification lab CEA - LETI 17 avenue des martyrs, 38054 Grenoble Cedex 9, France
Developer Samsung Electronics Co Ltd. 17 Floor, B-Tower, 1-1, Samsungjeonja-ro Hwaseong-si, Gyeonggi-do 445-330, Corée du Sud Commanditaire Samsung Electronics Co Ltd. 17 Floor, B-Tower, 1-1, Samsungjeonja-ro Hwaseong-si, Gyeonggi-do 445-330, Corée du Sud

References

Outgoing
  • ANSSI-CC-2017/16 - archived - SAMSUNG S3FV9QM / S3FV9QK rĂ©fĂ©rence : S3FV9QM/S3FV9QK rev3_TRCv1.0_PKALibv1.4-GUIv1.38a_DTRNGlibv2.0/3.0-Iv1.2_BLv2.1/2.2-GUI1.2_BLv2.6-GUIv1.2.7_DOC-UMv1.11-SANv1.5-CDSv3.2
Incoming
  • ANSSI-CC-2021/02 - active - Samsung S3FV9QM/S3FV9QK 32-bit RISC Microcontroller for Smart Card with optional Secure RSA/ECC/SHA Libraries including specific IC Dedicated Software RĂ©fĂ©rence : S3FV9QM_20200504

Security target

Extracted keywords

Symmetric Algorithms
AES, DES, TDES, 3DES, Triple-DES, TDEA, HMAC
Asymmetric Algorithms
RSA-CRT, ECDH, ECDSA, ECC, Diffie-Hellman, DSA
Hash functions
SHA1, SHA224, SHA256, SHA384, SHA512
Schemes
Key Agreement
Protocols
PGP
Randomness
DTRNG, TRNG, RND, RNG
Elliptic Curves
P-192, P-224, P-256, P-384, P-521, secp192k1, secp192r1, secp224k1, secp224r1, secp256k1, secp256r1, secp384r1, secp521r1, brainpoolP192r1, brainpoolP192t1, brainpoolP224r1, brainpoolP224t1, brainpoolP256r1, brainpoolP256t1, brainpoolP320r1, brainpoolP320t1, brainpoolP384r1, brainpoolP384t1, brainpoolP512r1, brainpoolP512t1
Block cipher modes
ECB

CPLC
IC Version
Vendor
Samsung

Security level
EAL5, EAL 4, EAL 5, EAL5 augmented, EAL 4 augmented, EAL 5 augmented
Claims
O.RNG, O.RND, O.MEM_ACCESS, T.RND
Security Assurance Requirements (SAR)
ADV_ARV, ADV_FSP, ADV_IMP, ADV_VAN, ADV_ARC.1, ADV_FSP.5, ADV_IMP.1, ADV_INT.2, ADV_TDS.4, ADV_FSP.4, ADV_TDS.3, AGD_OPE, AGD_PRE, AGD_OPE.1, AGD_PRE.1, ALC_DVS.2, ALC_DEL, ALC_DVS, ALC_CMS, ALC_CMC, ALC_CMC.4, ALC_CMS.5, ALC_DEL.1, ALC_LCD.1, ALC_TAT.2, ALC_DVS.1, ALC_CMS.4, ATE_COV, ATE_COV.2, ATE_DPT.3, ATE_FUN.1, ATE_IND.2, ATE_DPT.1, AVA_VAN.5, ASE_CCL.1, ASE_ECD.1, ASE_INT.1, ASE_OBJ.2, ASE_REQ.2, ASE_SPD.1, ASE_TSS.1
Security Functional Requirements (SFR)
FAU_SAS, FAU_GEN, FAU_SAS.1, FAU_SAS.1.1, FAU_GEN.1, FCS_RNG, FCS_RNG.1, FCS_RNG.1.1, FCS_RNG.1.2, FCS_COP.1, FCS_COP, FCS_CKM.1, FCS_CKM.4, FCS_CKM, FCS_CKM.2, FDP_ACF, FDP_ITT.1, FDP_ITT.1.1, FDP_ACC.1, FDP_IFC.1, FDP_IFC.1.1, FDP_IFF.1, FDP_ACF.1, FDP_ACC.1.1, FDP_ACF.1.1, FDP_ACF.1.2, FDP_ACF.1.3, FDP_ACF.1.4, FDP_ITC.1, FDP_ITC.2, FDP_SDI.1, FDP_ACC, FDP_IFC, FDP_ITT, FMT_LIM, FMT_LIM.1, FMT_LIM.2, FMT_LIM.1.1, FMT_LIM.2.1, FMT_MSA.3, FMT_MSA.1, FMT_MSA.3.1, FMT_MSA.3.2, FMT_SMR.1, FMT_MSA.1.1, FMT_SMF.1, FMT_SMF.1.1, FMT_CKM.4, FMT_MSA, FMT_SMF, FPT_FLS.1, FPT_FLS.1.1, FPT_PHP.3, FPT_PHP.3.1, FPT_PHP, FPT_ITT.1, FPT_ITT.1.1, FPT_FLS, FPT_ITT, FRU_FLT.2, FRU_FLT.1, FRU_FLT
Protection profiles
BSI-PP-0035

Side-channel analysis
Leak-Inherent, Physical Probing, physical probing, Physical probing, side-channel, side channel, DPA, SPA, timing attacks, timing attack, physical tampering, Malfunction, malfunction, DFA, reverse engineering

Standards
FIPS PUB 180-3, FIPS 197, BSI-AIS31, AIS31, AIS 31, CCMB-2017-04-001, CCMB-2017-04-004, CCMB-2017-04-002, CCMB-2017-04-003

File metadata

Title Security Target
Creation date D:20180606113443+09'00'
Modification date D:20181127163657+01'00'
Pages 72
Creator Microsoft® Word 2010
Producer Microsoft® Word 2010

Heuristics

Automated inference - use with caution

All attributes shown in this section (e.g., links between certificates, products, vendors, and known CVEs) are generated by automated heuristics and have not been reviewed by humans. These methods can produce false positives or false negatives and should not be treated as definitive without independent verification. For details on our data sources and inference methods, see our methodology. If you believe any information here is inaccurate or harmful, please submit feedback.

Certificate ID

ANSSI-CC-2018/43

Extracted SARs

ADV_ARC.1, ADV_FSP.5, ADV_IMP.1, ADV_INT.2, ADV_TDS.4, AGD_OPE.1, AGD_PRE.1, ALC_CMC.4, ALC_CMS.5, ALC_DEL.1, ALC_DVS.2, ALC_LCD.1, ALC_TAT.2, ASE_CCL.1, ASE_ECD.1, ASE_INT.1, ASE_OBJ.2, ASE_REQ.2, ASE_SPD.1, ASE_TSS.1, ATE_COV.2, ATE_DPT.3, ATE_FUN.1, ATE_IND.2, AVA_VAN.5

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Showing 5 out of 59.

References

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Raw data

{
  "_type": "sec_certs.sample.cc.CCCertificate",
  "category": "Trusted Computing",
  "cert_link": null,
  "dgst": "49fdbc726cff0629",
  "heuristics": {
    "_type": "sec_certs.sample.cc.CCCertificate.Heuristics",
    "annotated_references": null,
    "cert_id": "ANSSI-CC-2018/43",
    "cert_lab": [
      "CEA"
    ],
    "cpe_matches": null,
    "direct_transitive_cves": null,
    "eal": "EAL5+",
    "extracted_sars": {
      "_type": "Set",
      "elements": [
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ALC_DEL",
          "level": 1
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ADV_IMP",
          "level": 1
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ALC_TAT",
          "level": 2
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ALC_CMS",
          "level": 5
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ATE_FUN",
          "level": 1
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ALC_CMC",
          "level": 4
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ATE_DPT",
          "level": 3
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ADV_TDS",
          "level": 4
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ADV_ARC",
          "level": 1
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ASE_CCL",
          "level": 1
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ASE_ECD",
          "level": 1
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ALC_DVS",
          "level": 2
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "AVA_VAN",
          "level": 5
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ATE_IND",
          "level": 2
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ASE_INT",
          "level": 1
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ALC_LCD",
          "level": 1
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "AGD_OPE",
          "level": 1
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "AGD_PRE",
          "level": 1
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ATE_COV",
          "level": 2
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ASE_TSS",
          "level": 1
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ADV_INT",
          "level": 2
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ASE_REQ",
          "level": 2
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ASE_SPD",
          "level": 1
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ADV_FSP",
          "level": 5
        },
        {
          "_type": "sec_certs.sample.sar.SAR",
          "family": "ASE_OBJ",
          "level": 2
        }
      ]
    },
    "extracted_versions": {
      "_type": "Set",
      "elements": [
        "32"
      ]
    },
    "indirect_transitive_cves": null,
    "next_certificates": null,
    "prev_certificates": null,
    "protection_profiles": {
      "_type": "Set",
      "elements": [
        "f6d23054061d72ba"
      ]
    },
    "related_cves": null,
    "report_references": {
      "_type": "sec_certs.sample.certificate.References",
      "directly_referenced_by": {
        "_type": "Set",
        "elements": [
          "ANSSI-CC-2021/02"
        ]
      },
      "directly_referencing": {
        "_type": "Set",
        "elements": [
          "ANSSI-CC-2017/16"
        ]
      },
      "indirectly_referenced_by": {
        "_type": "Set",
        "elements": [
          "ANSSI-CC-2021/02-R02",
          "ANSSI-CC-2021/02",
          "ANSSI-CC-2021/02-R01"
        ]
      },
      "indirectly_referencing": {
        "_type": "Set",
        "elements": [
          "ANSSI-CC-2014/22",
          "ANSSI-CC-2017/16",
          "ANSSI-CC-2014/75"
        ]
      }
    },
    "scheme_data": null,
    "st_references": {
      "_type": "sec_certs.sample.certificate.References",
      "directly_referenced_by": null,
      "directly_referencing": null,
      "indirectly_referenced_by": null,
      "indirectly_referencing": null
    },
    "verified_cpe_matches": null
  },
  "maintenance_updates": {
    "_type": "Set",
    "elements": []
  },
  "manufacturer": "Samsung Electronics Co., Ltd.",
  "manufacturer_web": "https://www.samsung.com",
  "name": "S3FV9QM/S3FV9QK 32-bit RISC Microcontroller for Smart Card with optional Secure RSA/ECC/SHA Library",
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