W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target I1 ##### W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G ###### Secure Flash Memory Security Target Publication date: 15-Dec-24 Page 1/44 W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target I1 ###### Contents | 1 | SECURITY TARGET INTRODUCTION..................................................................... | 5 | |---------------------------------------------------------------------------------------------------------------------------------|------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|-------------------------------------------------------------------------------------------------------------------| | 1.1 | SECURITY TARGET REFERENCE ............................................................................................. | 5 | | 1.2 | TOE REFERENCE | .............................................................................................................. 5 | | 1.3 | TOE OVERVIEW | ............................................................................................................... 6 | | 1.3.1 | TOE Type .............................................................................................................. | 6 | | 1.3.2 | TOE Intended Usage | .............................................................................................. 6 | | 1.3.3 | Non-TOE Hardware/Software/Firmware | ................................................................... 6 | | 1.4 TOE DESCRIPTION ........................................................................................................... | 1.4 TOE DESCRIPTION ........................................................................................................... | 7 | | 1.4.1 | Physical Scope | ....................................................................................................... 7 | | 1.4.2 | Logical Scope ....................................................................................................... | 11 | | 1.5 | TOE CONFIGURATIONS .................................................................................................... | 11 | | 1.6 | TOE LIFE CYCLE ............................................................................................................ | 12 | | 2 | CONFORMANCE CLAIM ....................................................................................... 13 | CONFORMANCE CLAIM ....................................................................................... 13 | | 2.1 | CC CONFORMANCE CLAIM................................................................................................. | 13 | | 2.2 | PP CLAIM ..................................................................................................................... | 13 | | 2.3 | PACKAGE CLAIM | ............................................................................................................. 13 | | | SECURITY PROBLEM DEFINITION ..................................................................... | 14 | | 3 | | | | 3.1 | ASSETS ........................................................................................................................ | 14 | | 3.1.1 | TSF data .............................................................................................................. | 14 | | 3.1.2 | User data ............................................................................................................. | 14 | | 3.2 | USERS / SUBJECTS .......................................................................................................... | 14 | | 3.3 | THREATS ...................................................................................................................... | 15 | | 3.4 | ORGANISATIONAL SECURITY POLICIES ................................................................................. | 16 | | 3.5 | ASSUMPTIONS ............................................................................................................... | 16 | | 4 | SECURITY OBJECTIVES ...................................................................................... | 17 | | 4.1 | SECURITY OBJECTIVES FOR THE TOE .................................................................................. | 17 | | 4.2 | SECURITY OBJECTIVES FOR THE OPERATIONAL ENVIRONMENT | ................................................... 19 | | 4.3 | SECURITY OBJECTIVES RATIONALE ...................................................................................... | 19 | | 4.3.1 | Threats ................................................................................................................ | 19 | | 4.3.2 | Assumptions ........................................................................................................ | 20 | | 4.3.3 | SPD and Security Objectives ................................................................................. | 20 | | 5 | EXTENDED REQUIREMENTS ............................................................................... | 23 | | 5.1 | EXTENDED FAMILIES | ....................................................................................................... 23 | | 5.1.1 | Extended Family FMT_LIM - Limited capabilities and availability .............................. | 23 | | 5.1.2 | Extended Family FDP_SDC - Stored data | confidentiality .......................................... 25 | | 6 | SECURITY REQUIREMENTS ................................................................................ | 27 | | 6.1 6.2 SECURITY | SECURITY FUNCTIONAL REQUIRMENTS RATIONAL ................................................................... FUNCTIONAL REQUIREMENTS | 27 ............................................................................... 27 | | | Malfunctions ........................................................................................................ | | | 6.2.1 | | 27 | | 6.2.2 | Abuse of Functionality .......................................................................................... | 28 | | 6.2.3 6.2.4 | Physical Manipulation and Probing ......................................................................... Leakage............................................................................................................... | 29 30 | | 6.2.5 | Secure Data Exchange .......................................................................................... | 31 | | 6.2.6 | Protection of Binding Key ...................................................................................... | 32 | Publication date: 15-Dec-24 Page 2/44 W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target I1 winbond | 6.3 | 6.3 | SECURITY ASSURANCE REQUIREMENTS ................................................................................. 33 | |-----------|----------------------------------------------------------------------------------------------------------------------------------|----------------------------------------------------------------------------------------------------------------------------------| | 6.4 | 6.4 | SECURITY REQUIREMENTS RATIONALE ................................................................................. 33 | | 6.4.1 | 6.4.1 | Objectives ........................................................................................................... 33 | | 6.4.2 | 6.4.2 | Rationale tables of Security Objectives and SFRs .................................................... 34 | | 6.4.3 | 6.4.3 | Dependencies ...................................................................................................... 36 | | 6.4.4 | 6.4.4 | Rationale for the Security Assurance Requirements ................................................ 38 | | 6.4.5 | 6.4.5 | ALC_DVS.2 Sufficiency of security measures .......................................................... 38 | | 6.4.6 | 6.4.6 | AVA_VAN.5 Advanced methodical vulnerability analysis .......................................... 38 | | 6.5 | ASSOCIATION TABLES OF SFRS AND TSS .............................................................................. 39 | ASSOCIATION TABLES OF SFRS AND TSS .............................................................................. 39 | | 7 | REVISIONS ......................................................................................................... 40 | REVISIONS ......................................................................................................... 40 | | 8 | ANNEX ................................................................................................................. 41 | ANNEX ................................................................................................................. 41 | | 8.1 | GLOSSARY .................................................................................................................... 41 | GLOSSARY .................................................................................................................... 41 | | 8.2 | ABBREVIATIONS ............................................................................................................. 41 | ABBREVIATIONS ............................................................................................................. 41 | | 8.3 INDEX | REFERENCES ................................................................................................................. 42 | ............................................................................................................................ 43 | Publication date: 15-Dec-24 Public Page 3/44 W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target I1 ####### Table of figures | Figure 1 TOE Architecture ............................................................................................................. 10 | |------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Table of tables | | Table 1 TOE Identification ............................................................................................................. 5 Table 2 TOE Physical Scope .......................................................................................................... 9 | | Table 3 TOE Configurations .......................................................................................................... 11 | | Table 5 TOE life-cycle .................................................................................................................. 12 | | Table 6 Threats and Security Objectives - Coverage ...................................................................... 20 | | Table 7 Security Objectives and Threats - Coverage ...................................................................... 21 | | Table 8 Security Objectives and OSPs - Coverage .......................................................................... 21 | | Table 9 Assumptions and Security Objectives for the Operational Environment - Coverage .............. 21 | | Table 10 Security Objectives for the Operational Environment and Assumptions - Coverage ............. 22 | | Table 11 Security Objectives and SFRs - Coverage ........................................................................ 35 | | Table 12 SFRs and Security Objectives ......................................................................................... 36 | | Table 13 SFRs Dependencies........................................................................................................ 36 Table 14 SARs Dependencies ....................................................................................................... 38 | | Table 15 SFRs and TSS - Coverage ............................................................................................... 39 | | Table 16 TSS and SFRs - Coverage ............................................................................................... 39 | | Table 17 History of Modifications .................................................................................................. 40 | Publication date: 15-Dec-24 Page 4/44 W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target I1 ####### 1 Security Target Introduction This introductory chapter contains the following sections: - Security Target Reference - TOE Reference - TOE Overview - TOE Description - TOE operating modes and life-cycle This Security Target is based on the Security IC Platform Protection Profile with Augmentation Packages [5]. However, the Security Target does not include the Random Generation and the IC Identification security objectives. The corresponding assumptions of the Protection Profile are not used and replaced by other assumptions. On the other hand, the Security Target includes additional elements which are not required by the Protection Profile [5]. Those security elements (threats, security objectives, SFR) are clearly identified in each Chapter of this document. ## 1.1 Security Target Reference Title: W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target Version: I1 Authors: Winbond Technology Ltd. Evaluator: Applus Certified by: CCN Organismo de Certificacion ## 1.2 TOE Reference The Target of Evaluation is identified as below: Table 1 TOE Identification | Commercial Name | SpiFlash® TrustME ™ Secure Flash Memory | |-------------------|--------------------------------------------------------| | Product Name | W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G | | Version | AA | | Guidance | Refer to table 2 | Publication date: 15-Dec-24 Page 5/44 W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target I1 ## 1.3 TOE Overview ### 1.3.1 TOE Type The Target of Evaluation is a Memory Flash IC. ### 1.3.2 TOE Intended Usage The TOE is dedicated to be embedded into highly critical hardware devices such as smart card, secure element, USB token, secure micro SD, etc. These devices will embed secure applications such as financial, telecommunication, identity (e-Government), etc and will be working in a hostile environment. In particular, the TOE is dedicated to the secure storage of the code and data of critical applications. The security needs for the TOE consist in: - Maintaining the integrity of the content of the memories and the confidentiality of the content of protected memory areas as required by the critical HW products (e.g. Security IC) the Memory Flash is built for; - Providing a secure communication with the Host device that will embed the TOE in a secure HW product such as Security IC; ### 1.3.3 Non-TOE Hardware/Software/Firmware For the present ST, the TOE is a pure storage hardware device. The TOE does not comprise: - a) The Host device that will embed the TOE and will be needed to run the TOE in order to stimulate the TSF. - b) SPI Bus for the communication between the Host device and the TOE. The ST assumes that all components (Hardware or Software) of the Host Device are appropriately protected in the TOE security environment. Publication date: 15-Dec-24 Page 6/44 W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target I1 ## 1.4 TOE Description ### 1.4.1 Physical Scope The TOE comprises: - All security functionality necessary to ensure the secure execution of the Memory Flash: | No | Type | Identifier | Part Number 1 | Delivery Method | Notes | |-----------------------------------------|-----------------------------------------|-----------------------------------------|-----------------------------------------|-------------------|---------------------------------------------| | Form of delivery: Known Good Die Device | Form of delivery: Known Good Die Device | Form of delivery: Known Good Die Device | Form of delivery: Known Good Die Device | | | | 1 | HW | IC Part number | W75F40W WIB | Via Courier | 4Mb, 1.8V, Wafer Form, Industrial, | | 2 | HW | IC Part number | W75F40W WJB | Via Courier | 4Mb, 1.8V, Wafer Form, Industrial Plus, | | 3 | HW | IC Part number | W75F40W WWB | Via Courier | 4Mb, 1.8V, Wafer Form, Wireless, | | 4 | HW | IC Part number | W75F40W WIC | Via Courier | 4Mb, 1.8V, Wafer Form, Industrial, | | 5 | HW | IC Part number | W75F40W WJC | Via Courier | 4Mb, 1.8V, Wafer Form, Industrial Plus, | | 6 | HW | IC Part number | W75F40W WWC | Via Courier | 4Mb, 1.8V, Wafer Form, Wireless, | | 7 | HW | IC Part number | W75F40WR IB | Via Courier | 4Mb, 1.8V, RDL Wafer Form, Industrial, | | 8 | HW | IC Part number | W75F40WR JB | Via Courier | 4Mb, 1.8V, Wafer Form, Industrial Plus, | | 9 | HW | IC Part number | W75F40WR WB | Via Courier | 4Mb, 1.8V, RDL Wafer Form, Wireless, | | 10 | HW | IC Part number | W75F40WR IC | Via Courier | 4Mb, 1.8V, RDL Wafer Form, Industrial, | | 11 | HW | IC Part number | W75F40WR JC | Via Courier | 4Mb, 1.8V, RDL Wafer Form, Industrial Plus, | | 12 | HW | IC Part number | W75F40WR WC | Via Courier | 4Mb, 1.8V, RDL Wafer Form, Wireless, | Publication date: 15-Dec-24 Public Page 7/44 W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target I1 ### w winbond | No | Type | Identifier | Part Number 1 | Delivery Method | Notes | |------------------------------------|------------------------------------|------------------------------------|------------------------------------|------------------------------------|---------------------------------------------------| | Form of delivery: Assembled Device | Form of delivery: Assembled Device | Form of delivery: Assembled Device | Form of delivery: Assembled Device | Form of delivery: Assembled Device | Form of delivery: Assembled Device | | 1 | HW | IC Part number | W75F40WB YICG | Via Courier | 4Mb, 1.8V, WLCSP, Industrial, Green package | | 2 | HW | IC Part number | W75F40W Q3ICG | Via Courier | 4Mb, 1.8V, QFN32, Industrial, Green package | | 3 | HW | IC Part number | W75F40WB YIBG | Via Courier | 4Mb, 1.8V, WLCSP, Industrial, Green package | | 4 | HW | IC Part number | W75F40W Q3IBG | Via Courier | 4Mb, 1.8V, QFN32, Industrial, Green package | | 5 | HW | IC Part number | W75F40WB YWCG | Via Courier | 4Mb, 1.8V, WLCSP, Wireless, Green package | | 6 | HW | IC Part number | W75F40W Q3WCG | Via Courier | 4Mb, 1.8V, QFN32, WirelessGreen package | | 7 | HW | IC Part number | W75F40WB YWBG | Via Courier | 4Mb, 1.8V, WLCSP, Wireless, Green package | | 8 | HW | IC Part number | W75F40W Q3WBG | Via Courier | 4Mb, 1.8V, QFN32, Wireless, Green package | | 9 | HW | IC Part number | W75F40WB YJCG | Via Courier | 4Mb, 1.8V, WLCSP, Industrial plus, Green package | | 10 | HW | IC Part number | W75F40W Q3JCG | Via Courier | 4Mb, 1.8V, QFN32, Industrial plus, Green package | | 11 | HW | IC Part number | W75F40WB YJBG | Via Courier | 4Mb, 1.8V, WLCSP, Industrial plus, Green package | | 12 | HW | IC Part number | W75F40W Q3JBG | Via Courier | 4Mb, 1.8V, QFN32, Industrial plusI, Green package | ####### Form of delivery: Associated IC Dedicated Documentation | No | Type | Identifier | Versi on | Delivery Method | Full Name | Hash | Notes | |------|--------|-----------------------------------------|------------|-------------------|-----------------------------------------|--------------------------------------------------------------------|---------| | 1 | PDF | W75F40Wxx Bx AGD Preparative User Guide | C | Encrypted mail | W75F40Wxx Bx_AGD_PR E_RevC_21N ov23.pdf | db882c00381109c682943d 5e8529eda73ccbb5f907e52 863bdfa4f5641b5966f | | | 2 | PDF | W75F40Wxx Cx AGD Preparative User Guide | C | Encrypted mail | W75F40Wxx Cx_AGD_PR E_RevC_21N ov23.pdf | 2fab87fc33a77b354c463ac 8a90f76472594f163fe697d 03e1473d738dba21e2 | | | 3 | PDF | W75F40Wxx Bx AGD Operational User Guide | B | Encrypted mail | W75F40Wxx Bx_AGD_OP E_RevB_14J un23.pdf | e07c660c0ccfd1a9ee5b487 6441b1f0c501b7f83039e7f 1139d454a8ac2adeb2 | | | 4 | PDF | W75F40Wxx Cx AGD | B | Encrypted mail | W75F40Wxx Cx_AGD_OP E_RevB_14J un23.pdf | 6b830089fbda5db400d3cdc 05378979c5201579b30018 a5a83094920df6eb6e2 | | Publication date: 15-Dec-24 Public Page 8/44 W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target I1 Table 2 TOE Physical Scope | No | Type | Identifier | Part Number 1 | Part Number 1 | Delivery Method | Delivery Method | Notes | Notes | Notes | |------|--------|-----------------------------------------------|-----------------------------------------------|-----------------|-------------------|--------------------------------------------------------|--------------------------------------------------------|---------------------------------------------------------------------|---------| | | | Operational User Guide | Operational User Guide | | | | | | | | 5 | PDF | W75F40Wxx Cx/W75F40 WxxBx Secure Flash | W75F40Wxx Cx/W75F40 WxxBx Secure Flash | A5 | Mail | W75F40Wxx Bx_W75F40 WxxCx_Data sheet_RevA5 _20Nov23.pd | W75F40Wxx Bx_W75F40 WxxCx_Data sheet_RevA5 _20Nov23.pd | 2bb12f23755aa3690240 c8e9817c070d4ca38218 8668eb095ba5a545d00 5c17e | For all | | 6 | PDF | Datasheet SFI IP Functional Specification | Datasheet SFI IP Functional Specification | A2 | Encrypted mail | SFI3_FS_v3. 22_RevA2_2 10728.pdf | SFI3_FS_v3. 22_RevA2_2 10728.pdf | 85e21393db862cd3c7b51fb 4802bcf22ddb91739d7276 005aa7c719797da7e34 | For all | | 7 | PDF | W75F Pre- Binding Application | W75F Pre- Binding Application | B | Encrypted mail | W75F Pre- Binding AN RevB 11May23.pdf | W75F Pre- Binding AN RevB 11May23.pdf | 4e2063aec42fd25940c16dc497 328b2847afc0688034db1369d4 6a2fb6de6601 | | | 8 | PDF | Note HUID to pre- Binding Key mapping formula | Note HUID to pre- Binding Key mapping formula | N/A | Encrypted mail | N/A | N/A | N/A | | #### 1.4.1.1 TOE Physical Characteristics The TOE physical characteristics are described as follows. ####### Performance 50MHz Standard/Dual/Quad SPI clocks 20.5 MB/S continuous encrypted and authenticated data transfer rate More than 100,000 erase/program cycles More than 20-year data retention ####### Efficiency 16-byte burst read Data Integrity Check Allows secure execution in place (S-XIP) operation ####### Operating conditions - o Single 1.62 to 1.98V supply - o 20mA active current, <1 μ A Power-down (typ.) - o -40°C to +105°C operating range 1Mb-block Architecture Uniform Block Erase (4K-bytes) Publication date: 15-Dec-24 Public Page 9/44 W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target I1 Program 1 to 16 byte in a single command Erase/Program Suspend & Resume #### 1.4.1.2 TOE Architecture The architecture of the Memory Flash is described in Figure 1 . The TOE is delimited by the Red box. Figure 1 TOE Architecture The TOE consists of the following Hardware components: - Auxiliary array contains the flash specific data: - Flash array stores the User data (i.e. the mass data including executable codes) and translates SPI commands into Flash operations; - SFF (Secure Flash Front-end) which implements encrypted and authenticated interface for Flash operation and supports Flash memories up to 4GB; - Detectors of abnormal operating conditions; #### 1.4.1.3 Interfaces of the TOE - The physical interface of the TOE with the external environment is the entire surface of the Memory Flash module. - The electrical interface of the TOE with the external environment is made of the chip's pads including the data pins for SPI bus: - o Standard SPI: CLK, /CS, DI_IO0, DO_IO1 - o Dual SPI: CLK, /CS, DI_IO0, DO_IO1 - o Quad SPI: CLK, /CS, DI_IO0, DO_IO1, IO2, IO3 Publication date: 15-Dec-24 Public Page 10/44 W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target I1 ### 1.4.2 Logical Scope The main security features of the TOE are described as follows: - ⚫ Secure separation between Test mode and User mode. The confidentiality and the integrity of the flash content are protected - ⚫ The confidentiality and the integrity of the transmitted data from/to the Host device are protected by a secure channel; - ⚫ Integrity protection of the flash content by error detection codes - ⚫ Security sensors Active Shields against physical intrusive attacks); The logical interface of the TOE is made of Flash commands. ## 1.5 TOE Configurations | Part Number | Density | |---------------|-----------| | W75F40WxxBx | 4 Mbit | | W75F40WxxCx | 4 Mbit | ####### Table 3 TOE Configurations The guidance for the usage of the TOE, See table 2 Publication date: 15-Dec-24 Page 11/44 W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target I1 ## 1.6 TOE Life Cycle The development, manufacturing and integration processes of the TOE into a composite product can be separated into two distinct phases. Table 4 TOE life-cycle | Phase | Title | Description | |---------|---------------------------------|-------------------------------------------------------------------------------------------------------------| | 1 | TOE Development | Memory flash designer is responsible for: - TOE (HW) development | | 2 | TOE Manufacturing and Testing | Memory flash Manufacturer is responsible for: - Photomask manufacturing - wafer manufacturing and - testing | | 3 | TOE Packaging and Final Testing | Memory flash packaging: Memory flash final test: | The TOE is delivered as KGD (Known Good die) after phase 2 and in packaging form after phase 3. The TOE user is responsible for developing the Host-based dedicated driver. Publication date: 15-Dec-24 Page 12/44 W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target I1 ####### 2 Conformance Claim This chapter 2 contains the following sections: - CC Conformance Claim - PP Claim - Package Claim - Conformance Claim Rationale ## 2.1 CC Conformance Claim This Security target claims to be conformant to the Common Criteria version 3.1 Release 5. Furthermore, it claims to be CC Part 2 extended and CC Part 3 conformant. ## 2.2 PP Claim This Security Target does not claim conformance to any Protection Profile. ## 2.3 Package Claim The assurance level for this Security Target is EAL5 augmented with ALC_DVS.2 and AVA_VAN.5 because the TOE is dedicated to store highly critical applications and data which are submitted to advanced logical and physical attacks. Publication date: 15-Dec-24 Page 13/44 W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target I1 #### 3 Security Problem Definition ## 3.1 Assets Assets include all data stored in the TOE (including executable code of the applications). They include: - User data, that is typically stored in the "flash array" part of the memory chip; - TSF data, that is relied upon for the enforcement of the TOE security functionality. - o TSF data contains only sensitive data stored in registers or in the auxiliary array of the memory chip. Legacy registers are not part of the TSF (i.e. non-TSF). - o The TOE does not include any software, however the logic of the TOE security mechanisms is still part of the TSF data. This logic is hardcoded in SFF. ### 3.1.1 TSF data ####### TSF logic The TSF logic is the functionality of the TSF, and is hardcoded in the SFF component. The TSF logic is protected in terms of integrity and confidentiality. ####### Binding key (Kb) This key is protected in terms of integrity and confidentiality. ####### Runtime data The internal runtime data necessary for the execution of the SFF: All runtime data shall be protected in terms of integrity. All runtime data shall be protected in terms of confidentiality. ### 3.1.2 User data User data corresponds to all data stored inside the memory flash (including executable code of the applications). ####### User Data Mass data (including executable codes) stored in the "flash array" part of the memory chip. User data is protected in terms of integrity and confidentiality. ## 3.2 Users / Subjects ##### U.Host-Device The host device communicates with the TOE through a SPI Bus. Publication date: 15-Dec-24 Page 14/44 W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target I1 ## 3.3 Threats ##### T.Phys-Manipulation ####### Physical Manipulation An attacker may physically modify the Memory Flash in order to - o modify User Data stored in the TOE; - o modify TSF Data stored in the TOE; - o modify or deactivate the security services of the TOE (provided by TSF logic); - o modify the security mechanisms of the TOE (provided by TSF logic) to enable attacks disclosing or manipulating User Data, for example the integrity protection mechanism. ##### T.Phys-Probing ####### Physical Probing An attacker may perform physical probing of the TOE in order to disclose User Data and TSF Data while stored in Memory Flash. ##### T.Malfunction ####### Malfunction due to Environmental Stress An attacker may cause a malfunction of TSF logic by applying environmental stress in order to deactivate or affect security mechanisms of the TOE. This enables attacks disclosing or manipulating User Data. This may be achieved by operating the Memory Flash outside the normal operating conditions. ##### T.Abuse-Func ####### Abuse of Functionality An attacker may use functions of the TOE which may not be used after TOE Delivery in order to - o disclose or manipulate User Data (user data or code stored in the TOE) or - o enable an attack disclosing or manipulating User Data. ##### T.Leak-Inherent ####### Inherent Information Leakage An attacker may exploit information which is leaked from the TOE during usage of the Memory Flash in order to disclose confidential User Data. ##### T.Leak-Forced ####### Forced Information Leakage An attacker may exploit information which is leaked from the TOE during usage of the Memory Flash in order to disclose confidential User Data even if the information leakage is not inherent but caused by the attacker. Publication date: 15-Dec-24 Public Page 15/44 W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target I1 ##### T.Abuse-Communication ####### Communication Probing and Manipulation An attacker may probe and modify the communication between the TOE and U.HostDevice in order to manipulate User/TSF Data or disclose User/TSF Data read from the TOE. ##### T.Host-Forging ####### Forge the functionality of an authorized Host device An attacker may access to the User data currently stored in the TOE by: - o illegaly establishing a secure channel with the TOE (e.g. by tampering the Binding key or by forging the secure channel without knowing the Binding key) in order to execute the Flash commands; - o binding the TOE with another Host device in order to execute the Flash commands; ## 3.4 Organisational Security Policies N/A, there is no OSP. ## 3.5 Assumptions ##### A.Secure-Channel ####### External protection during the secure channel It is assumed that U.Host-Device supports the trusted communication channel with the TOE by protecting the confidentiality and the integrity of the transmitted data. In particular, U.Host-Device is assumed to correctly protect the secure channel in order to prevent data modification, disclosure, insertion, deletion and replaying. ##### A.Binding-Process ####### Protection during Binding process It is assumed that security procedures are used after delivery of the TOE by the TOE Manufacturer to maintain confidentiality and integrity of the TOE (to prevent any possible copy, modification, or unauthorised use). The confidentiality and authenticity of the binding process is guarentied by uniqe binding process. Publication date: 15-Dec-24 Page 16/44 W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target I1 ####### 4 Security Objectives ## 4.1 Security Objectives for the TOE This chapter contains the following sections: - Security Objectives for the TOE - Security Objectives for the operational Environment - Security Objectives Rationale ##### O.Phys-Probing ####### Protection against Physical Probing The TOE must provide protection against disclosure/reconstruction of User Data and TSF Data while stored in the Flash. This includes protection against - o measuring through galvanic contacts which is direct physical probing on the chips surface except on pads being bonded (using standard tools for measuring voltage and current) or - o measuring not using galvanic contacts but other types of physical interaction between charges (using tools used in solid-state physics research and IC failure analysis) with a prior reverse-engineering to understand the design and its properties and functions. The TOE must be designed and fabricated so that it requires a high combination of complex equipment, knowledge, skill, and time to be able to derive detailed design information or other information which could be used to compromise security through such a physical attack. ##### O.Malfunction ####### Protection against Malfunctions The TOE must ensure its correct operation. The TOE must indicate and prevent its operation outside the normal operating conditions where reliability and secure operation has not been proven or tested. This is to prevent malfunctions. Examples of environmental conditions are voltage, and clock frequency, temperature, or external energy fields. ##### O.Phys-Manipulation ####### Protection against Physical Manipulation The TOE must provide protection against manipulation of User Data (the user data stored in the TOE) and TSF data. This includes protection against - o reverse-engineering (understanding the design and its properties and functions), - o manipulation of the hardware and TSF data, as well as - o undetected manipulation of User data (i.e. Flash array). Publication date: 15-Dec-24 Page 17/44 W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target I1 ##### O.Abuse-Func ####### Protection against Abuse of Functionality The TOE must prevent that functions of the TOE which may not be used after TOE Delivery can be abused in order to (i) disclose sensitive user data stored in the TOE, (ii) manipulate sensitive user data stored in the TOE. ##### O.Leak-Inherent ####### Protection against Inherent Information Leakage The TOE must provide protection against disclosure of confidential data stored and processed in the TOE - o by measurement and analysis of the shape and amplitude of signals (for example on the power, clock, or I/O lines) and - o by measurement and analysis of the time between events found by measuring signals (for instance on the power, clock, or I/O lines). ##### O.Leak-Forced ####### Protection against Forced Information Leakage The TOE must be protected against disclosure of confidential data processed in the TOE (using methods as described under O.Leak-Inherent) even if the information leakage is not inherent but caused by the attacker - o by forcing a malfunction (refer to "Protection against Malfunction due to Environmental Stress O.Malfunction") and/or - o by a physical manipulation (refer to "Protection against Physical Manipulation - O.Phys-Manipulation"). If this is not the case, signals which normally do not contain significant information about secrets could become an information channel for a leakage attack. ##### O.Sec-Binding ####### Protection of residual information at Re-binding This objective protects against the disclosure of the User data when the TOE is re-bound to another Host device. This includes protection against: - o integrity failure on Binding Key - o illegal modification on Binding Key - o illegal attempt to erase the Binding key ##### O.Trusted-Path ####### Trusted communication with authorized Host The TSF provides a trusted path only with authorized U.Host-Device (based on the shared Binding key), and protects the confidentiality and the integrity of the User data /TSF data to be communicated with U.Host-Device . Publication date: 15-Dec-24 Page 18/44 W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target I1 ## 4.2 Security Objectives for the Operational Environment ####### OE.Secure-Channel ####### Secure communication with the TOE The authorized U.Host-Device shall support the trusted communication channel with the TOE by protecting the confidentiality and the integrity of the transmitted data. In particular, U.Host-Device shall correctly protect the secure channel in order to prevent data modification, disclosure, insertion, deletion and replaying. ####### OE.Binding-Process ####### Protection during Binding process Security procedures shall be used after the TOE delivery to maintain confidentiality and integrity of the TOE (to prevent any possible copy, modification, retention, theft or unauthorised use). ## 4.3 Security Objectives Rationale ### 4.3.1 Threats - T.Phys-Manipulation This threat is countered by the security objectives O.PhysManipulation. This objective ensures that the protection against manipulation of the user data is provided by the TOE. - T.Phys-Probing This threat is countered by the security objectives O.Phys-Probing. This objective ensures that the protection against disclosure/reconstruction of User Data and TSF Data while stored in the Flash is provided by the TOE. - T.Malfunction This threat is countered by the security objectives O.Malfunction. This objective ensures the correct operation of the TOE outside the normal operating conditions. - T.Abuse-Func This threat is countered by the security objectives O.Abuse-Func. This objective prevents that functions of the TOE which may not be used after TOE Delivery can be abused in order to manipulate/disclose sensitive user data stored in the TOE. - T.Leak-Inherent This threat is countered by the security objectives O.Leak-Inherent. This objective ensures the protection against disclosure of confidential data stored and processed in the TOE. - T.Leak-Forced This threat is countered by the security objectives O.Leak-Forced. This objective ensures the protection against disclosure of confidential data stored and Publication date: 15-Dec-24 Page 19/44 W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target I1 processed in the TOE even if the information leakage is not inherent but caused by the attacker. - T.Abuse-Communication This threat is countered by the security objective O.Trusted-Path. This objective protects the confidentiality and the integrity of the User/TSF data to be communicated with U.Host-Device. - T.Host-Forging This threat is countered by the security objectives: - o O.Trusted-Path to protect the confidentiality and the integrity of the User data to be communicated with U.Host-Device. - o O.Sec-Binding to protect against the disclosure of the User data when the TOE is rebound to another Host device ### 4.3.2 Assumptions - A.Secure-Channel Since OE.Secure-Channel requires the Host device to implement the protection assumed in A.Secure-Channel, the assumption is covered by this objective. - A.Binding-Process Since OE.Binding-Process requires the Composite Product Manufacturer to implement those measures assumed in A.Binding-Process, the assumption is covered by this objective. ### 4.3.3 SPD and Security Objectives Table 5 Threats and Security Objectives - Coverage | Threats | Security Objectives | Rationale | |-----------------------|-------------------------------|---------------| | T.Phys-Manipulation | O.Phys-Manipulation | Section 4.3.1 | | T.Phys-Probing | O.Phys-Probing | Section 4.3.1 | | T.Malfunction | O.Malfunction | Section 4.3.1 | | T.Abuse-Func | O.Abuse-Func | Section 4.3.1 | | T.Leak-Inherent | O.Leak-Inherent | Section 4.3.1 | | T.Leak-Forced | O.Leak-Forced | Section 4.3.1 | | T.Abuse-Communication | O.Trusted-Path | Section 4.3.1 | | T.Host-Forging | O.Trusted-Path, O.Sec-Binding | Section 4.3.1 | Publication date: 15-Dec-24 Page 20/44 W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target I1 Table 6 Security Objectives and Threats - Coverage | Security Objectives | Threats | Threats | |-----------------------|--------------------------------|---------------------| | O.Phys-Probing | T.Phys-Probing | T.Phys-Probing | | O.Malfunction | T.Malfunction | T.Malfunction | | O.Phys- Manipulation | T.Phys-Manipulation | T.Phys-Manipulation | | O.Abuse-Func | T.Abuse-Func | T.Abuse-Func | | O.Leak-Inherent | T.Leak-Inherent | T.Leak-Inherent | | O.Leak-Forced | T.Leak-Forced | T.Leak-Forced | | O.Sec-Binding | T.Host-Forging | T.Host-Forging | | O.Trusted-Path | T.Abuse-Communication, Forging | T.Host- | | OE.Secure-Channel | | | | OE.Binding-Process | | | Table 7 Security Objectives and OSPs - Coverage | Security Objectives | |-----------------------| | O.Phys-Probing | | O.Malfunction | | O.Phys- Manipulation | | O.Abuse-Func | | O.Leak-Inherent | | O.Leak-Forced | | O.Sec-Binding | | O.Trusted-Path | | OE.Secure-Channel | | OE.Binding-Process | Table 8 Assumptions and Security Objectives for the Operational Environment - Coverage | Assumptions | Security Objectives for the Operational Environment | Rationale | |-------------------|-------------------------------------------------------|---------------| | A.Secure-Channel | OE.Secure-Channel | Section 4.3.2 | | A.Binding-Process | OE.Binding-Process | Section 4.3.2 | Publication date: 15-Dec-24 Public Page 21/44 W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target I1 | Security Objectives Environment | for | the Operational | Assumptions | |-----------------------------------|-------|-------------------|--------------------| | OE.Secure-Channel | | | A.Secure- Channel | | OE.Binding-Process | | | A.Binding- Process | Table 9 Security Objectives for the Operational Environment and Assumptions - Coverage Publication date: 15-Dec-24 Page 22/44 W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target I1 ####### 5 Extended Requirements ## 5.1 Extended Families ### 5.1.1 Extended Family FMT_LIM - Limited capabilities and availability #### 5.1.1.1 Description To define the IT security functional requirements of the TOE an additional family (FMT_LIM) of the Class FMT (Security Management) is defined here. This family describes the functional requirements for the Test Features of the TOE. The new functional requirements were defined in the class FMT because this class addresses the management of functions of the TSF. The examples of the technical mechanism used in the TOE (refer to Section 6.2) appropriate to address the specific issues of preventing the abuse of functions by limiting the capabilities of the functions and by limiting their availability. The family "Limited capabilities and availability (FMT_LIM)" is specified as follows. ####### FMT_LIM Limited capabilities and availability Family behaviour This family defines requirements that limit the capabilities and availability of functions in a combined manner. Note that FDP_ACF restricts the access to functions whereas the component Limited Capability of this family requires the functions themselves to be designed in a specific manner. Component levelling: FMT_LIM.1 Limited capabilities requires that the TSF is built to provide only the capabilities (perform action, gather information) necessary for its genuine purpose. FMT_LIM.2 Limited availability requires that the TSF restrict the use of functions (refer to Limited capabilities (FMT_LIM.1)). This can be achieved, for instance, by removing or by disabling functions in a specific phase of the TOE's life-cycle. Publication date: 15-Dec-24 Page 23/44 W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target I1 Management: FMT_LIM.1, FMT_LIM.2 There are no management activities foreseen. Audit: FMT_LIM.1, FMT_LIM.2 There are no actions defined to be auditable. #### 5.1.1.2 Extended Components ####### Extended Component FMT_LIM.1 ####### Description Limited capabilities requires that the TSF is built to provide only the capabilities (perform action, gather information) necessary for its genuine purpose. Hierarchical to: No other components. Definition ####### FMT_LIM.1 Limited capabilities FMT_LIM.1.1 The TSF shall be designed and implemented in a manner that limits its capabilities so that in conjunction with "Limited availability (FMT_LIM.2)" the following policy is enforced [assignment: Limited capability policy]. Dependencies: (FMT_LIM.2) ####### Extended Component FMT_LIM.2 Description Limited availability requires that the TSF restrict the use of functions (refer to Limited capabilities (FMT_LIM.1)). This can be achieved, for instance, by removing or by disabling functions in a specific phase of the TOE's life-cycle. Publication date: 15-Dec-24 Page 24/44 W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target I1 Hierarchical to: No other components. Definition ####### FMT_LIM.2 Limited availability - FMT_LIM.2.1 The TSF shall be designed in a manner that limits its availability so that in conjunction with "Limited capabilities (FMT_LIM.1)" the following policy is enforced [assignment: Limited availability policy]. Dependencies: (FMT_LIM.1) ####### Application Note: The functional requirements FMT_LIM.1 and FMT_LIM.2 assume that there are two types of mechanisms (limitation of capabilities and limitation of availability) which together shall provide protection in order to enforce the same policy or two mutual supportive policies related to the same functionality. This allows e.g. that - (i) the TSF is provided without restrictions in the product in its user environment but its capabilities are so limited that the policy is enforced or conversely - (ii) the TSF is designed with high functionality but is removed or disabled in the product in its user environment. ### 5.1.2 Extended Family FDP_SDC - Stored data confidentiality #### 5.1.2.1 Description To define the security functional requirements of the TOE an additional family (FDP_SDC.1) of the Class FDP (User data protection) is defined here. The family "Stored data confidentiality (FDP_SDC)" is specified as follows. ####### FDP_SDC Stored data confidentiality ####### Family behaviour This family provides requirements that address protection of user data confidentiality while these data are stored within memory areas protected by the TSF. The TSF provides access to the data in the memory through the specified interfaces only and prevents compromise of their information bypassing these interfaces. It complements the family Stored data integrity (FDP_SDI) which protects the user data from integrity errors while being stored in the memory. Component levelling: Publication date: 15-Dec-24 Page 25/44 W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target I1 FDP_SDC.1 Requires the TOE to protect the confidentiality of information of the user data in specified memory areas. Management: FDP_SDC.1 There are no management activities foreseen. Audit: FDP_SDC.1 There are no actions defined to be auditable. #### 5.1.2.2 Extended Components ####### Extended Component FDP_SDC.1 Description Requires the TOE to protect the confidentiality of information of the user data in specified memory areas. Hierarchical to: No other components. Definition ####### FDP_SDC.1 Stored data confidentiality FDP_SDC.1.1 The TSF shall ensure the confidentiality of the information of the user data while it is stored in the [assignment: memory areas] . Dependencies: No dependencies. Publication date: 15-Dec-24 Page 26/44 W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target I1 ####### 6 Security Requirements ## 6.1 Security Functional Requirments Rational In order to define the Security Functional Requirements Part 2 of the Common Criteria was used. However, some Security Functional Requirements have been refined. The refinements are described below the associated SFR: The refinement operation is used to add detail to a requirement, and, thus, further restricts a requirement. In such a case a extra paragraph starting with "Refinement" may be given. The selection operation is used to select one or more options provided by the CC in stating a requirement. Selections having been made by the ST author are denoted as bold and italicized. The assignment operation is used to assign a specific value to an unspecified parameter, such as the length of a password. Assignments having been made by the ST author appear in bold text. The iteration operation is used when a component is repeated with varying operations. Iteration is denoted by showing a slash "/", and the iteration indicator after the component identifier. ## 6.2 Security Functional Requirements ### 6.2.1 Malfunctions ####### FRU_FLT.2 Limited fault tolerance FRU_FLT.2.1 The TSF shall ensure the operation of all the TOE's capabilities when the following failures occur: [assignment: list of type of failures]. The TSF shall ensure the operation of all the TOE's capabilities when the following failures occur: exposure to operating conditions which are not detected according to the requirement Failure with preservation of secure state (FPT_FLS.1/Detectors) . ####### Application Note: The term "failure" above means "circumstances". The TOE prevents failures for the "circumstance" defined above. Publication date: 15-Dec-24 Page 27/44 W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target I1 ####### FPT_FLS.1/Detectors Failure with preservation of secure state FPT_FLS.1.1/Detectors The TSF shall preserve a secure state when the following types of failures occur: [assignment : list of types of failures in the TSF]. The TSF shall preserve a secure state when the following types of failures occur: - o Out-of-specified range voltage - o Out-of-specified range temperature - o Out-of specified range clock frequency - o Power glitch. ####### Application Note: The term "failure" above means "circumstances". The TOE prevents failures for the "circumstance" defined above. The secure state is maintained by TSF's detectors. The TSF's detectors monitor the failures. If a failure happens, the TSF disturbs the cryptographic computations, interrupts data interchange and inform U.Host-Device . ### 6.2.2 Abuse of Functionality ####### FMT_LIM.1 Limited capabilities FMT_LIM.1.1 The TSF shall be designed and implemented in a manner that limits its capabilities so that in conjunction with "Limited availability (FMT_LIM.2)" the following policy is enforced [assignment : Limited capability policy ]. The TSF shall be designed and implemented in a manner that limits its capabilities so that in conjunction with "Limited availability (FMT_LIM.2)" the following policy is enforced Deploying Test Features after TOE Delivery does not allow user data to be disclosed or manipulated, TSF data to be disclosed or manipulated, and no substantial information about construction of TSF to be gathered which may enable other attacks. ####### Application Note: In the Test mode, the following restrictions are enforced by the TSF: - The Binding Key (Kb) cannot be read out by the Flash commands; - The Binding key cannot be erased unless a complete erase has been done after the last reset; - The read and write commands do not read and write effective values of the flash array; Publication date: 15-Dec-24 Page 28/44 W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target I1 ####### FMT_LIM.2 Limited availability FMT_LIM.2.1 The TSF shall be designed in a manner that limits its availability so that in conjunction with "Limited capabilities (FMT_LIM.1)" the following policy is enforced [assignment: Limited availability policy] . The TSF shall be designed in a manner that limits its availability so that in conjunction with "Limited capabilities (FMT_LIM.1)" the following policy is enforced Deploying Test Features after TOE Delivery does not allow user data to be disclosed or manipulated, TSF data to be disclosed or manipulated, and no substantial information about construction of TSF to be gathered which may enable other attacks. Application Note: The switch from User mode to Test mode is allowed after TOE delivery but after the flash array is completely erased. ### 6.2.3 Physical Manipulation and Probing ####### FDP_SDC.1 Stored data confidentiality - FDP_SDC.1.1 The TSF shall ensure the confidentiality of the information of the user data while it is stored in the [assignment : memory areas ] . The TSF shall ensure the confidentiality of the information of the user data while it is stored in the Flash array . ####### FDP_SDI.2 Stored data integrity monitoring and action FDP_SDI.2.1 The TSF shall monitor user data stored in containers controlled by the TSF for [assignment : integrity errors] on all objects, based on the following attributes: [assignment : user data attributes ] . The TSF shall monitor user data stored in containers controlled by the TSF for CRC-32 error detecting code on all objects, based on the following attributes: stored in the Flash array with CRC-32 and read via authenticated read . FDP_SDI.2.2 Upon detection of a data integrity error, the TSF shall [assignment : action to be taken ] . Upon detection of a data integrity error, the TSF shall inform U.Host-Device about the error. In addition, the TSF also sends a pseudo-randomly chosen part of the CRC32 error detecting bits to U.Host-Device in a secure manner so that data integrity can be independently verified by U.Host-Device. Publication date: 15-Dec-24 Public Page 29/44 W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target I1 ####### FPT_PHP.3 Resistance to physical attack FPT_PHP.3.1 The TSF shall resist [assignment : physical tampering scenarios ] to the [assignment : list of TSF devices/elements ] by responding automatically such that the SFRs are always enforced. The TSF shall resist physical manipulation and physical probing to the TSF by responding automatically such that the SFRs are always enforced. ####### Application Note: The TSF will implement appropriate mechanisms to continuously counter physical manipulation and physical probing. Due to the nature of these attacks (especially manipulation) the TSF can by no means detect attacks on all of its elements. Therefore, permanent protection against these attacks is required ensuring that security functional requirements are enforced. Hence, "automatic response" means here (i) assuming that there might be an attack at any time and (ii) countermeasures are provided at any time. ### 6.2.4 Leakage ####### FDP_ITT.1 Basic internal transfer protection FDP_ITT.1.1 The TSF shall enforce the [assignment : access control SFP(s) and/or information flow control SFP(s)] to prevent the [selection: disclosure, modification, loss of use] of user data when it is transmitted between physically-separated parts of the TOE. The TSF shall enforce the Data Processing Policy to prevent the disclosure of user data when it is transmitted between physically-separated parts of the TOE. ####### Application Note: The Flash array and the SFF are seen as physically-separated parts of the TOE. ####### FPT_ITT.1 Basic internal TSF data transfer protection FPT_ITT.1.1 The TSF shall protect TSF data from [selection: disclosure, modification] when it is transmitted between separate parts of the TOE. The TSF shall protect TSF data from disclosure when it is transmitted between separate parts of the TOE. Application Note: Publication date: 15-Dec-24 Public The Flash array and the SFF are seen as physically-separated parts of the TOE. Page 30/44 W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target I1 ####### FDP_IFC.1 Subset information flow control FDP_IFC.1.1 The TSF shall enforce the [assignment : information flow control SFP ] on [assignment: list of subjects, information, and operations that cause controlled information to flow to and from controlled subjects covered by the SFP ] . The TSF shall enforce the Data Processing Policy on User data that is processed or transferred by the TOE or by U.Host-Device . ####### Application Note: The following Security Function Policy (SFP) Data Processing Policy is defined for the requirement "Subset information flow control (FDP_IFC.1)" "User data and TSF data shall not be accessible from the TOE except when the U.Host-Device decides to communicate the User data via an external interface". ### 6.2.5 Secure Data Exchange ####### FDP_UCT.1 Basic data exchange confidentiality FDP_UCT.1.1 The TSF shall enforce the [assignment: access control SFP(s) and/or information flow control SFP(s)] to [selection: transmit, receive] user data in a manner protected from unauthorised disclosure. The TSF shall enforce the Data Processing Policy to receive and transmit user data in a manner protected from unauthorised disclosure. ####### FDP_UIT.1 Data exchange integrity FDP_UIT.1.1 The TSF shall enforce the [assignment: access control SFP(s) and/or information flow control SFP(s)] to [selection: transmit, receive] user data in a manner protected from [selection: modification, deletion, insertion, replay] errors. The TSF shall enforce the Data Processing Policy to transmit and receive user data in a manner protected from replay, modification, deletion and insertion errors. FDP_UIT.1.2 The TSF shall be able to determine on receipt of user data, whether [selection: modification, deletion, insertion, replay] has occurred. The TSF shall be able to determine on receipt of user data, whether replay, modification, deletion and insertion has occurred. Publication date: 15-Dec-24 Page 31/44 W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target I1 ####### FTP_TRP.1 Trusted path FTP_TRP.1.1 The TSF shall provide a communication path between itself and [selection: remote, local] users that is logically distinct from other communication paths and provides assured identification of its end points and protection of the communicated data from [selection: modification, disclosure, [assignment: other types of integrity or confidentiality violation ] ]. The TSF shall provide a communication path between itself and remote users that is logically distinct from other communication paths and provides assured identification of its end points and protection of the communicated data from modification and disclosure . FTP_TRP.1.2 The TSF shall permit [selection: the TSF, local users, remote users] to initiate communication via the trusted path. The TSF shall permit remote users to initiate communication via the trusted path. FTP_TRP.1.3 The TSF shall require the use of the trusted path for [selection: initial user authentication, [assignment: other services for which trusted path is required]]. The TSF shall require the use of the trusted path for any access to User data stored in the Flash array . ### 6.2.6 Protection of Binding Key ####### FPT_FLS.1/Binding_Key Failure with preservation of secure state FPT_FLS.1.1/Binding_Key The TSF shall preserve a secure state when the following types of failures occur: [assignment: list of types of failures in the TSF ] . The TSF shall preserve a secure state when the following types of failures occur: integrity failure on Binding Key . ####### FDP_RIP.1 Subset residual information protection FDP_RIP.1.1 The TSF shall ensure that any previous information content of a resource is made unavailable upon the [selection: allocation of the resource to, deallocation of the resource from] the following objects: [assignment: list of objects ]. Refinement: The TSF shall ensure that any previous information content of the Flash array is made unavailable upon the allocation of the resource to and deallocation of the resource from the following objects: the Binding key (Kb) . Publication date: 15-Dec-24 Public Page 32/44 W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target I1 ####### Application Note: - "Object Allocation" means that a new Binding key is set in order to replace the current Binding key. - "Object Deallocation" means that the current Binding key is erased from the TSF (more precisely, from the auxiliary array). ## 6.3 Security Assurance Requirements The Evaluation Assurance Level is EAL5 augmented with ALC_DVS.2 and AVA_VAN.5. ## 6.4 Security Requirements Rationale ### 6.4.1 Objectives #### 6.4.1.1 Security Objectives for the TOE - O.Phys-Probing The SFR FDP_SDC.1 requires the TSF to protect the confidentiality of the user data stored in specified memory areas and prevent its compromise by physical attacks bypassing the specified interfaces for memory access. The scenario of physical probing as described for this objective is explicitly included in the assignment chosen for the physical tampering scenarios in FPT_PHP.3. Therefore, it is clear that this security functional requirement supports the objective. - O.Malfunction The definition of this objective shows that it covers a situation, where malfunction of the TOE might be caused by the operating conditions of the TOE (while direct manipulation of the TOE is covered O.Phys-Manipulation). There are two possibilities in this situation: Either the operating conditions are inside the tolerated range or at least one of them is outside of this range. The second case is covered by FPT_FLS.1/Detectors, because it states that a secure state is preserved in this case. The first case is covered by FRU_FLT.2 because it states that the TOE operates correctly under normal (tolerated) conditions. - O.Phys-Manipulation The SFR FDP_SDI.2 requires the TSF to detect the integrity errors of the stored user data and react in case of detected errors. More precisely, FDP_SDI.2 prevents manipulation of memory contents by ensuring detection and response from the TSF. The scenario of physical manipulation as described for this objective is explicitly included in the assignment chosen for the physical tampering scenarios in FPT_PHP.3. Therefore, it is clear that this security functional requirement supports the objective. - O.Abuse-Func This objective states that abuse of functions (especially provided by the IC Dedicated Test Software, for instance in order to read secret data) must not be possible when TOE is used by the final user. There are two possibilities to achieve this: (i) They cannot be used by an attacker (i. e. its availability is limited) or (ii) using them would not Publication date: 15-Dec-24 Page 33/44 W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target I1 be of relevant use for an attacker (i. e. its capabilities are limited) since the functions are designed in a specific way. The first possibility is specified by FMT_LIM.2 and the second one by FMT_LIM.1. Since these requirements are combined to support the policy, which is suitable to fulfil O.Abuse-Func, both security functional requirements together are suitable to meet the objective. Other security functional requirements (FPT_ITT.1, FDP_ITT.1, FPT_PHP.3, FRU_FLT.2, FPT_FLS.1/Detectors and FDP_IFC.1) which prevent attackers from circumventing the functions implementing these two security functional requirements (for instance by manipulating the hardware) also support the objective. The relevant objectives are O.Leak-Inherent, O.Phys-Probing, O.Malfunction, O.Phys-Manipulation, O.Leak-Forced. - O.Leak-Inherent The security functional requirements FPT_ITT.1 and FDP_ITT.1 together with the policy statement in FDP_IFC.1 explicitly require the prevention of disclosure of secret data (TSF data as well as user data) when while being processed. This includes that attackers cannot reveal such data by measurements of emanations, power consumption or other behaviour of the TOE while data is processed by TOE parts. - O.Leak-Forced This objective is directed against attacks, where an attacker wants to force an information leakage, which would not occur under normal conditions. In order to achieve this the attacker has to combine a first attack step, which modifies the behaviour of the TOE (either by exposing it to extreme operating conditions or by directly manipulating it) with a second attack step measuring and analysing some output produced by the TOE. The first step is prevented by the same mechanisms which support O.Malfunction (FPT_FLS.1/Detectors, FRU_FLT.2) and O.Phys-Manipulation (FPT_PHP.3), respectively. The requirements covering O.Leak-Inherent (FPT_ITT.1, FDP_ITT.1, FDP_IFC.1) also support O.Leak-Forced because they prevent the attacker from being successful if he tries the second step directly. - O.Sec-Binding The security functional requirement FDP_RIP.1 ensures that the User data is erased before the Host device is changed. The security functional requirement FPT_FLS.1/Binding_Key protects against integrity failure on Binding Key and illegal modification on Binding Key - O.Trusted-Path The security functional requirement FTP_TRP.1 contribute in this protection because it only establishes a trusted path between the TSF and authorized U.Host-Device for the communication purpose. The security functional requirement FPT_FLS.1/Binding_Key protects the Binding key against the tampering. The security functional requirements FDP_UCT.1 and FDP_UIT.1 protect against the modification (integrity) and the disclosure (confidentiality) of the User data communication between the TSF and U.Host-Device . ### 6.4.2 Rationale tables of Security Objectives and SFRs | Security Objectives | Security Functional Requirements | Rationale | |-----------------------|------------------------------------|-------------| | O.Phys-Probing | FPT_PHP.3, FDP_SDC.1 | Section | | | | 6.4.1.1 | Publication date: 15-Dec-24 Public Page 34/44 W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target I1 Table 10 Security Objectives and SFRs - Coverage | Security Objectives | Security Functional Requirements | Rationale | |-----------------------|--------------------------------------------------------------------------------------------------|-----------------| | O.Malfunction | FRU_FLT.2, FPT_FLS.1/Detectors | Section 6.4.1.1 | | O.Phys- Manipulation | FDP_SDI.2, FPT_PHP.3 | Section 6.4.1.1 | | O.Abuse-Func | FDP_ITT.1, FPT_ITT.1, FPT_PHP.3, FRU_FLT.2, FPT_FLS.1/Detectors, FMT_LIM.1, FMT_LIM.2, FDP_IFC.1 | Section 6.4.1.1 | | O.Leak-Inherent | FDP_ITT.1, FPT_ITT.1, FDP_IFC.1 | Section 6.4.1.1 | | O.Leak-Forced | FDP_ITT.1, FPT_ITT.1, FRU_FLT.2, FPT_FLS.1/Detectors, FPT_PHP.3, FDP_IFC.1 | Section 6.4.1.1 | | O.Sec-Binding | FDP_RIP.1, FPT_FLS.1/Binding_Key | Section 6.4.1.1 | | O.Trusted-Path | FDP_UCT.1, FDP_UIT.1, FPT_FLS.1/Binding_Key, FTP_TRP.1 | Section 6.4.1.1 | | Security Functional Requirements | Security Objectives | Security Objectives | Security Objectives | |------------------------------------|---------------------------------------------|-----------------------|-----------------------| | FRU_FLT.2 | O.Malfunction, Forced | O.Abuse-Func, | O.Leak- | | FPT_FLS.1/Detectors | O.Malfunction, Forced | O.Abuse-Func, | O.Leak- | | FMT_LIM.1 | O.Abuse-Func | | | | FMT_LIM.2 | O.Abuse-Func | | | | FDP_SDC.1 | O.Phys-Probing | | | | FDP_SDI.2 | O.Phys-Manipulation | | | | FPT_PHP.3 | O.Phys-Probing, O.Abuse-Func, O.Leak-Forced | O.Phys-Manipulation, | O.Phys-Manipulation, | | FDP_ITT.1 | O.Abuse-Func, Forced | O.Leak-Inherent, | O.Leak- | | FPT_ITT.1 | O.Abuse-Func, Forced | O.Leak-Inherent, | O.Leak- | | FDP_IFC.1 | O.Abuse-Func, Forced | O.Leak-Inherent, | O.Leak- | | FDP_UCT.1 | O.Trusted-Path | | | | FDP_UIT.1 | O.Trusted-Path | | | | FTP_TRP.1 | O.Trusted-Path | | | Publication date: 15-Dec-24 Page 35/44 W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target I1 Table 11 SFRs and Security Objectives | Security Functional Requirements | Security Objectives | |------------------------------------|-------------------------------| | FPT_FLS.1/Binding_Key | O.Trusted-Path, O.Sec-Binding | | FDP_RIP.1 | O.Sec-Binding | ### 6.4.3 Dependencies #### 6.4.3.1 SFRs Dependencies Table 12 SFRs Dependencies | Requirements | CC Dependencies | Satisfied Dependencies | |-----------------------|---------------------------------------------------|--------------------------| | FRU_FLT.2 | (FPT_FLS.1) | FPT_FLS.1/Detectors | | FPT_FLS.1/Detectors | No Dependencies | | | FMT_LIM.1 | (FMT_LIM.2) | FMT_LIM.2 | | FMT_LIM.2 | (FMT_LIM.1) | FMT_LIM.1 | | FDP_SDC.1 | No Dependencies | | | FDP_SDI.2 | No Dependencies | | | FPT_PHP.3 | No Dependencies | | | FDP_ITT.1 | (FDP_ACC.1 or FDP_IFC.1) | FDP_IFC.1 | | FPT_ITT.1 | No Dependencies | | | FDP_IFC.1 | (FDP_IFF.1) | | | FDP_UCT.1 | (FDP_ACC.1 or FDP_IFC.1) (FTP_ITC.1 or FTP_TRP.1) | and FDP_IFC.1, FTP_TRP.1 | | FDP_UIT.1 | (FDP_ACC.1 or FDP_IFC.1) (FTP_ITC.1 or FTP_TRP.1) | and FDP_IFC.1, FTP_TRP.1 | | FTP_TRP.1 | No Dependencies | | | FPT_FLS.1/Binding_Key | No Dependencies | | | FDP_RIP.1 | No Dependencies | | Rationale for the exclusion of Dependencies The dependency FDP_IFF.1 of FDP_IFC.1 is discarded. Part 2 of the Common Criteria defines the dependency of FDP_IFC.1 (information flow control policy statement) on FDP_IFF.1 (Simple security attributes). The specification of FDP_IFF.1 would not capture the nature of the security functional requirement nor add any detail. As stated in the Data Processing Policy referred to in FDP_IFC.1, there are no attributes necessary. The security functional requirement for the TOE is sufficiently described using FDP_ITT.1 and its Data Processing Policy (FDP_IFC.1). Publication date: 15-Dec-24 Public Page 36/44 W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target I1 #### 6.4.3.2 SARs Dependencies | Requirements | CC Dependencies | CC Dependencies | CC Dependencies | Satisfied Dependencies | Satisfied Dependencies | |----------------|-------------------------------------------------|-----------------------------|-------------------------------------------------|--------------------------------------------|----------------------------------| | ADV_ARC.1 | (ADV_FSP.1) and (ADV_TDS.1) | (ADV_FSP.1) and (ADV_TDS.1) | (ADV_FSP.1) and (ADV_TDS.1) | ADV_FSP.5, ADV_TDS.4 | ADV_FSP.5, ADV_TDS.4 | | ADV_FSP.5 | (ADV_IMP.1) and (ADV_TDS.1) | (ADV_IMP.1) and (ADV_TDS.1) | (ADV_IMP.1) and (ADV_TDS.1) | ADV_IMP.1, ADV_TDS.4 | ADV_IMP.1, ADV_TDS.4 | | ADV_IMP.1 | (ADV_TDS.3) and (ALC_TAT.1) | (ADV_TDS.3) and (ALC_TAT.1) | (ADV_TDS.3) and (ALC_TAT.1) | ADV_TDS.4, ALC_TAT.2 | ADV_TDS.4, ALC_TAT.2 | | ADV_INT.2 | (ADV_IMP.1) (ALC_TAT.1) | and | (ADV_TDS.3) and | ADV_IMP.1, ALC_TAT.2 | ADV_TDS.4, | | ADV_TDS.4 | (ADV_FSP.5) | (ADV_FSP.5) | (ADV_FSP.5) | ADV_FSP.5 | ADV_FSP.5 | | AGD_OPE.1 | (ADV_FSP.1) | (ADV_FSP.1) | (ADV_FSP.1) | ADV_FSP.5 | ADV_FSP.5 | | AGD_PRE.1 | No Dependencies | No Dependencies | No Dependencies | | | | ALC_CMC.4 | (ALC_CMS.1) (ALC_LCD.1) | and (ALC_DVS.1) | and | ALC_CMS.5, ALC_LCD.1 | ALC_DVS.2, | | ALC_CMS.5 | No Dependencies | No Dependencies | No Dependencies | | | | ALC_DEL.1 | No Dependencies | No Dependencies | No Dependencies | | | | ALC_DVS.2 | No Dependencies | No Dependencies | No Dependencies | | | | ALC_LCD.1 | No Dependencies | No Dependencies | No Dependencies | | | | ALC_TAT.2 | (ADV_IMP.1) | (ADV_IMP.1) | (ADV_IMP.1) | ADV_IMP.1 | ADV_IMP.1 | | ASE_CCL.1 | (ASE_ECD.1) (ASE_REQ.1) | and | (ASE_INT.1) and | ASE_ECD.1, ASE_REQ.2 | ASE_INT.1, | | ASE_ECD.1 | No Dependencies | No Dependencies | No Dependencies | | | | ASE_INT.1 | No Dependencies | No Dependencies | No Dependencies | | | | ASE_OBJ.2 | (ASE_SPD.1) | (ASE_SPD.1) | (ASE_SPD.1) | ASE_SPD.1 | ASE_SPD.1 | | ASE_REQ.2 | (ASE_ECD.1) and (ASE_OBJ.2) | (ASE_ECD.1) and (ASE_OBJ.2) | (ASE_ECD.1) and (ASE_OBJ.2) | ASE_ECD.1, ASE_OBJ.2 | ASE_ECD.1, ASE_OBJ.2 | | ASE_SPD.1 | No Dependencies | No Dependencies | No Dependencies | | | | ASE_TSS.1 | (ADV_FSP.1) (ASE_REQ.1) | and | (ASE_INT.1) and | ADV_FSP.5, ASE_REQ.2 | ASE_INT.1, | | ATE_COV.2 | (ADV_FSP.2) and (ATE_FUN.1) | (ADV_FSP.2) and (ATE_FUN.1) | (ADV_FSP.2) and (ATE_FUN.1) | ADV_FSP.5, ATE_FUN.1 | ADV_FSP.5, ATE_FUN.1 | | ATE_DPT.3 | (ADV_ARC.1) (ATE_FUN.1) | and | (ADV_TDS.4) and | ADV_ARC.1, ATE_FUN.1 | ADV_TDS.4, | | ATE_FUN.1 | (ATE_COV.1) | (ATE_COV.1) | (ATE_COV.1) | ATE_COV.2 | ATE_COV.2 | | ATE_IND.2 | (ADV_FSP.2) (AGD_PRE.1) (ATE_FUN.1) | and and | (AGD_OPE.1) and (ATE_COV.1) and | ADV_FSP.5, AGD_PRE.1, ATE_FUN.1 | AGD_OPE.1, ATE_COV.2, | | AVA_VAN.5 | (ADV_ARC.1) (ADV_IMP.1) (AGD_OPE.1) (ATE_DPT.1) | and and and | (ADV_FSP.4) and (ADV_TDS.3) and (AGD_PRE.1) and | ADV_ARC.1, ADV_IMP.1, AGD_OPE.1, ATE_DPT.3 | ADV_FSP.5, ADV_TDS.4, AGD_PRE.1, | Publication date: 15-Dec-24 Page 37/44 W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target I1 ####### Table 13 SARs Dependencies ### 6.4.4 Rationale for the Security Assurance Requirements The assurance level EAL5 and the augmentation with the requirements ALC_DVS.2, and AVA_VAN.5 were chosen in order to meet assurance expectations explained in the following paragraphs. An assurance level of EAL5 with the augmentations AVA_VAN.5 and ALC_DVS.2 are required for this type of TOE since it is intended to defend against sophisticated attacks. This evaluation assurance package was selected to permit a developer to gain maximum assurance from positive security engineering based on good commercial practices. In order to provide a meaningful level of assurance that the TOE provides an adequate level of defence against such attacks, the evaluators should have access to the low level design and source code. ### 6.4.5 ALC_DVS.2 Sufficiency of security measures Development security is concerned with physical, procedural, personnel and other technical measures that may be used in the development environment to protect the TOE. In the particular case of a memory flash the TOE is developed and produced within a complex and distributed industrial process which must especially be protected. Details about the implementation, (e.g. from design, test and development tools as well as Initialisation Data) may make such attacks easier. Therefore, in the case of a memory flash, maintaining the confidentiality of the design is very important. This assurance component is a higher hierarchical component to EAL5 (which only requires ALC_DVS.1). ALC_DVS.2 has no dependencies. ### 6.4.6 AVA_VAN.5 Advanced methodical vulnerability analysis Due to the intended use of the TOE, it must be shown to be highly resistant to penetration attacks. This assurance requirement is achieved by the AVA_VAN.5 component. Independent vulnerability analysis is based on highly detailed technical information. The main intent of the evaluator analysis is to determine that the TOE is resistant to penetration attacks performed by an attacker possessing high attack potential. AVA_VAN.5 has dependencies to ADV_ARC.1 "Security architecture description", ADV_FSP.2 "Security enforcing functional specification", ADV_TDS.3 "Basic modular design", ADV_IMP.1 "Implementation representation of the TSF", AGD_OPE.1 "Operational user guidance", and AGD_PRE.1 "Preparative procedures". All these dependencies are satisfied by EAL5. It has to be assumed that attackers with high attack potential try to attack memory flashes embedded in smart cards used for digital signature applications or payment systems. Therefore, specifically AVA_VAN.5 was chosen in order to assure that even these attackers cannot successfully attack the TOE. Publication date: 15-Dec-24 Page 38/44 W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target I1 Publication date: 15-Dec-24 winbond ## 6.5 Association tables of SFRs and TSS Table 14 SFRs and TSS - Coverage | Security Functional Requirements | TOE Summary Specification | |------------------------------------|-----------------------------------------| | FRU_FLT.2 | SF.OPE-COND | | FPT_FLS.1/Detectors | SF.OPE-COND | | FMT_LIM.1 | SF.OPE-MODE | | FMT_LIM.2 | SF.OPE-MODE | | FDP_SDC.1 | SF.PHY-PRO, SF.SEC-MEM-CONF | | FDP_SDI.2 | SF.PHY-PRO, SF.SEC-MEM-INT | | FPT_PHP.3 | SF.PHY-PRO | | FDP_ITT.1 | SF.PHY-PRO | | FPT_ITT.1 | SF.PHY-PRO | | FDP_IFC.1 | SF.SEC-MEM-CONF, SF.SEC-COM, SF.PHY-PRO | | FDP_UCT.1 | SF.SEC-COM | | FDP_UIT.1 | SF.SEC-COM | | FTP_TRP.1 | SF.SEC-AUTH | | FPT_FLS.1/Binding_Key | SF.KEY-PRO | | FDP_RIP.1 | SF.KEY-PRO | Table 15 TSS and SFRs - Coverage | TOE Specification | Summary Security Functional Requirements | |---------------------|------------------------------------------------------------------| | SF.SEC-COM | FDP_IFC.1, FDP_UCT.1, FDP_UIT.1 | | SF.PHY-PRO | FDP_SDC.1, FDP_SDI.2, FPT_PHP.3, FDP_ITT.1, FPT_ITT.1, FDP_IFC.1 | | SF.OPE-MODE | FMT_LIM.1, FMT_LIM.2 | | SF.OPE-COND | FRU_FLT.2, FPT_FLS.1/Detectors | | SF.SEC-MEM-INT | FDP_SDI.2 | | SF.SEC-MEM-CONF | FDP_SDC.1, FDP_IFC.1 | | SF.KEY-PRO | FPT_FLS.1/Binding_Key, FDP_RIP.1 | | SF.SEC-AUTH | FTP_TRP.1 | Public Page 39/44 W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target I1 ####### 7 Revisions Table 16 History of Modifications | Modification | Comment | |----------------|---------------| | A | New version | | I | Final version | | I1 | Lite version | Publication date: 15-Dec-24 Page 40/44 W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target I1 ####### 8 ANNEX ## 8.1 Glossary ####### SFI Secure Flash Interface is the SPI interface on the Host device (i.e. SPI Master). ####### SFF Secure Flash Front-end is the SPI interface on the memory chip (i.e. SPI Slave). ####### SPI Serial Peripheral Interface is a synchronous serial data link, a de facto standard, that operates in full duplex mode. ## 8.2 Abbreviations CC Common Criteria EAL Evaluation Assurance Level IT Information Technology PP Protection Profile ST Security Target TOE Target of Evaluation TSC TSF Scope of Control TSF TOE Security Functionality TSFI TSF Interface TSP TOE Security Policy Publication date: 15-Dec-24 Page 41/44 W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target I1 ## 8.3 References - [1] Common Criteria, Part 1: Common Criteria for Information Technology Security Evaluation, Part 1: Introduction and General Model, Version 3.1, Revision 5, April 2017, CCMB-201704-001 - [2] Common Criteria, Part 2: Common Criteria for Information Technology Security Evaluation, Part 2: Security Functional Components, Version 3.1, Revision 5, April 2017, CCMB-201704-002 - [3] Common Criteria, Part 3: Common Criteria for Information Technology Security Evaluation, Part 3: Security Assurance Components, Version 3.1, Revision 5, April 2017, CCMB-201704-003 - [4] Common Methodology for Information Technology Security Evaluation, Evaluation Methodology, Version 3.1, Revision 5, April 2017, CCMB-2017-04-004 - [5] Eurosmart, Security IC Platform with Augmentation Packages, Version 1.0, February 2014, BSI-PP-0084. - [6] Winbond Technology Ltd., SpiFlash 1.8V secure flash memory Datasheet. - [7] Winbond Technology Ltd., N/A. - [8] Joint Interpretation Library: Application of Attack Potential to Smartcards, Nov 2022, Version 3.2. - [9] Supporting Document, Mandatory Technical Document: The Application of CC to Integrated Circuits, March 2009, Version 3.0, Revision 1, CCDB-2009-03-002 - [10] Supporting Document Guidance: Smartcard Evaluation, February 2010, Version 2.0, CCDB-2010-03-001 - [11] Supporting Document Guidance Security Architecture requirements (ADV_ARC) for smart cards and similar devices, July 2021, Version 2.1, - [12] N/A - [13] Supporting Document Mandatory Technical Document: Application of Attack Potential to Smartcards July 2020, Version 3.0. - [14] Supporting Document: Composite product evaluation for Smart Cards and similar devices, May 2018, Version 2.1 - [15] Joint Interpretation Library: Minimum Site Security Requirements, Ver 3.0, Feb 2020 - [16] ISO/IEC 7816-3. Identification cards - integrated circuit cards. Part 3: Cards with contacts Electrical interface and transmission protocols. Publication date: 15-Dec-24 Page 42/44 W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target I1 ####### Index | A | A | |------------------------------------------------------------------------|----------------------------------------------------------------| | A.Binding-Process | ............................................... 17 | | A.Secure-Channel | ................................................ 17 | | B | B | | Binding__key__(Kb) ............................................ | 15 | | F | F | | FDP_IFC.1 | ........................................................... 30 | | FDP_ITT.1 | ........................................................... 30 | | FDP_RIP.1 ........................................................... | 32 | | FDP_SDC.1 .......................................................... | 29 | | FDP_SDI.2 ........................................................... | 29 | | FDP_UCT.1 | ......................................................... 31 | | FDP_UIT.1 ........................................................... | 31 | | FMT_LIM.1 | ......................................................... 28 | | FMT_LIM.2 | ......................................................... 28 | | FPT_FLS.1/Binding_Key .................................... | 32 | | FPT_FLS.1/Detectors ........................................... | 27 | | FPT_ITT.1 ............................................................ | 30 | | FPT_PHP.3 | .......................................................... 29 | | FRU_FLT.2 | .......................................................... 27 | | FTP_TRP.1 | .......................................................... 31 | | O | O | | O.Abuse-Func ...................................................... | 18 | | O.Leak-Forced ..................................................... | 19 | | O.Leak-Inherent ................................................... | 19 | | O.Malfunction ...................................................... | 18 | | O.Phys-Manipulation | ........................................... 18 | | O.Phys-Probing | .................................................... 18 | | O.Sec-Binding ...................................................... | 19 | Publication date: 15-Dec-24 O.Trusted-Path ...................................................... 19 OE.Binding-Process .............................................. 20 OE.Secure-Channel ............................................... 19 R Runtime__data ...................................................... 15 S SF.KEY-PRO ........................................................ 59 SF.OPE-COND ..................................................... 58 SF.OPE-MODE .................................................... 58 SF.PHY-PRO ........................................................ 57 SF.SEC-AUTH ..................................................... 59 SF.SEC-COM ....................................................... 57 SF.SEC-MEM-CONF ........................................... 58 SF.SEC-MEM-INT ............................................... 58 T T.Abuse-Communication ...................................... 16 T.Abuse-Func ....................................................... 16 T.Host-Forging ..................................................... 17 T.Leak-Forced ....................................................... 16 T.Leak-Inherent .................................................... 16 T.Malfunction ....................................................... 16 T.Phys-Manipulation ............................................ 16 T.Phys-Probing ..................................................... 16 TSF__logic............................................................ 15 U U.Host-Device ...................................................... 15 User__Data ........................................................... 15 Page 43/44 W75F40W[W/R][I/J/W][B/C] & W75F40W[BY/Q3][I/J/W][C/B]G Secure Flash Memory Security Target I1 ####### Preliminary Designation The "Preliminary" designation on a Winbond datasheet indicates that the product is not fully characterized. The specifications are subject to change without notice and are not guaranteed. Winbond or an authorized sales representative should be consulted for current information before using this product. ####### Trademarks Winbond , SpiFlash and TrustME are trademarks of Winbond Electronics Corporation . All other marks are the property of their respective owner. ####### Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Furthermore, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. Information in this document is provided solely in connection with Winbond products. Winbond reserves the right to make changes, corrections, modifications or improvements to this document and the products and services described herein at any time, without notice. Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this datasheet belong to their respective owners. Publication date: 15-Dec-24 Page 44/44