1
DMT-CBS-CE3D3 Security Target Lite
DATANG MICROELECTRONICS TECHNOLOGY Co., Ltd
Security Target Lite
DATANG MICROELECTRONICS TECHNOLOGY Co., Ltd.
29 August 2016
Version 0.9
DMT-CBS-CE3D3 Family (DMT-CBS-CE3D3/CC080/CC048)
Dual interface smart card chip with HAL library version 1.0
Security Target Lite
DMT-CBS-CE3D3 Security Target Lite
DATANG MICROELECTRONICS TECHNOLOGY Co., Ltd.
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Document History
Change By
Initial version Jing Yang
Modify editorial changes Jing Yang
Update for the formal evaluation Jing Yang
Release for final version Jing Yang
Xiangshan Zhang
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Contents
1 ST Introduction .................................................................................................................. 1
1.1. ST identifiers................................................................................................................ 1
1.2. TOE overview .............................................................................................................. 1
1.3. TOE description ........................................................................................................... 2
1.3.1. Physical scope ....................................................................................................... 2
1.3.2 Logical scope......................................................................................................... 3
1.3.3 TOE components................................................................................................... 3
1.4 Life cycle and delivery................................................................................................. 3
2. Conformance claim ............................................................................................................ 5
2.1. CC Conformance.......................................................................................................... 5
2.2. PP Claim....................................................................................................................... 5
2.3. Package claim............................................................................................................... 5
2.4. Conformance claim rationale ....................................................................................... 5
3. Security problem definition................................................................................................ 6
3.1. Description of Assets ................................................................................................... 6
3.2. Threats.......................................................................................................................... 6
3.3. Organisational security policies ................................................................................... 6
3.4. Assumptions................................................................................................................. 7
4. Security objectives ............................................................................................................. 8
4.1. Security objectives for the TOE................................................................................... 8
4.2. Security objectives for the security IC embedded software......................................... 8
4.3. Security objectives for the operational environment.................................................... 9
4.4. Security objectives rationale ........................................................................................ 9
5. Extended Components Definitions................................................................................... 10
6. Security requirements....................................................................................................... 11
6.1. Definitions.................................................................................................................. 11
6.2. Security Functional Requirements (SFR) .................................................................. 11
6.2.1. SFRs derived from the Security IC Platform Protection Profile......................... 11
6.2.2. SFRs regarding cryptographic functionality ....................................................... 14
6.3. Security Assurance Requirements (SAR) .................................................................. 15
6.4. Security requirements rationale.................................................................................. 16
6.4.1. Security Functional Requirements (SFR) ........................................................... 16
6.4.2. Dependencies of the SFRs................................................................................... 17
6.4.3. Security Assurance Requirements (SAR) ........................................................... 18
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7. TOE summary specification............................................................................................. 19
7.1. Malfunction ................................................................................................................ 19
7.2. Leakage ...................................................................................................................... 19
7.3. Physical manipulation and probing............................................................................ 19
7.4. Abuse of functionality and Identification................................................................... 20
7.5. Random numbers........................................................................................................ 20
7.6. Cryptographic functionality ....................................................................................... 20
8. References ........................................................................................................................ 21
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1 ST Introduction
This Security Target (ST) is built upon the Security IC Platform Protection Profile with
Augmentation Packages [1]. Registered and Certified by Bundesamt für Sicherheit in der
Informations technik (BSI) under the reference BSI-CC-PP-0084-2014.
This chapter presents the ST reference, the reference for the Target of Evaluation (TOE), a
TOE overview description and a description of the logical and physical scope of the TOE.
1.1. ST identifiers
ST reference: DMT-CBS-CE3D3 Family (DMT-CBS-CE3D3/CC080/CC048) Dual
Interface smart card chips with HAL library version 1.0 Security Target,
29 August 2016, version 0.9
TOE reference: DMT-CBS-CE3D3 Family (DMT-CBS-CE3D3/CC080/CC048) Dual
Interface smart card chips with HAL library version 1.0
1.2. TOE overview
The DMT-CBS-CE3D3 Family (DMT-CBS-CE3D3/CC080/CC048) TOE is a dual interface
smart card chips (80kB EEPROM size for DMT-CBS-CE3D3/CC080 and 48kB EEPROM
size for DMT-CBS-CE3D3/CC048) suitable for instance to support a Java Card OS, ID cards,
Banking card, etc.
The TOE consists of hardware and IC dedicated software. The hardware is based on a 32-bit
CPU with ROM (Non-Volatile Read-Only Memory), EEPROM (Non-volatile Programmable
Memory) and RAM (Volatile Memory). The hardware of the TOE also incorporates
communication peripherals and cryptographic coprocessors for execution and acceleration of
symmetric and asymmetric cryptographic algorithms. The IC dedicated software contains a
library of cryptographic services.
The TOE supports the following communication interfaces:
 ISO/IEC 14443 TYPE A/B contactless interface
 ISO/IEC 7816 contact interface.
The TOE is delivered to a composite product manufacturer. The security IC embedded
software is developed by the composite product manufacturer. The security IC embedded
software is sent to Datang to be implemented in ROM and delivered back to the composite
product manufacturer together with the TOE.
The TOE has been designed to provide a platform for Security IC Embedded Software which
ensures that the critical user data of the Composite TOE are stored and processed in a secure
way. To this end the TOE has the following security features:
 Hardware coprocessor for TDES
 Hardware coprocessor for AES
 True Random Number Generator
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 Hardware for RSA support
 Protection against side channel analysis
 Protection against physical attacks,
 Protection against perturbation attacks,
 HAL library with cryptographic services
The above features can be controlled by the Security IC embedded software. The software
library in the IC dedicated software has been designed to provide easy access to the hardware
functions and to complement these.
1.3. TOE description
This section presents the physical and logical scope of the TOE.
1.3.1. Physical scope
A block diagram of the TOE hardware is depicted below.
ROM320KB
EEPROM
80KB/48KB
ARM
SC000
CPU
Environmental
Detectors
SRAM10KB
TEST
CryptoRAM
2KB
Vcc
Reset
Clock
I/O
TDES
bignumber
CRC
AES
IS014443
TypeA/B
RF
PMU
ISO7816
TRNG
Watch
dog
OSC
Timer
ResetGen
ClockGen
AC0
AC1
AHB
decode
AHB
bus
for
memory
AHB
bus
for
SFR
SHA-1
Domestic
algorithms
The hardware of the TOE has the following components:
 ARM SC000 CPU
 80kB EEPROM for DMT-CBS-CE3D3/CC080
48kB EEPROM for DMT-CBS-CE3D3/CC048
 320kB ROM
 12kB RAM
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 ISO/IEC 14443 Type A/B contactless interface
 ISO/IEC 7816 contact interface supports T=0/T=1 protocol
 CRC co-processor
 True Random Number Generator
 Hardware crypto peripherals
o DES
o AES
o Bignumber for RSA support
o SHA-1
o Domestic algorithms
 Hardware security circuitry
 Detector Circuitry
1.3.2 Logical scope
The TOE provides the following Security IC dedicated software, which is used by the
Security IC embedded software to perform critical operations.
The Security IC dedicated Support software provides the following security functions:
· TDES cryptographic function
· AES cryptographic function
· RSA cryptographic function
· Random Number Generation
The TOE provides the single DES and SHA-1 algorithms that only support the correctness of
the functionality.
The domestic algorithms are existent in the TOE, but these domestic algorithms only support
the correctness of the functionality.
1.3.3 TOE components
The TOE consists of the following components that are delivered to the composite product
manufacturer:
Type Name Version Package
Hardware DMT-CBS-CE3D3 Family
(DMT-CBS-CE3D3/CC080/CC048)
V1.0 die, module
Software HAL V1.0 Software library
Document Preparative Procedures V1.2 document
Operational User Guidance V1.6 document
1.4 Life cycle and delivery
The end-consumer environment of the TOE is phase 7 of the Security IC product life-cycle as
defined in the PP [1]. In this phase the TOE is in usage by the end-consumer. Its method of
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use now depends on the Security IC Embedded Software. Examples of use cases are ID cards
or Bank cards.
The scope of the assurance components referring to the TOE’s life cycle is limited to phases
2, 3 and 4. These phases are under the control of the TOE manufacturer. At the end of phase 4
the TOE components described in 1.3.3 are delivered to the Composite Manufacturer.
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2. Conformance claim
This chapter presents conformance claim and the conformance claim rationale.
2.1. CC Conformance
This Security Target and TOE claims to be conformant to the Common Criteria version 3.1:
• Part 1 revision 4 [2].
• Part 2 revision 4 [3]
• Part 3 revision 4 [4]
For the evaluation will be used the methodology in Common Criteria Evaluation
Methodology version 3.1 CEM revision 4 [5]
This Security Target and TOE claims to be CC Part 2 extended and CC Part 3 conformant.
2.2. PP Claim
This Security Target claims strict conformance to the Security IC Platform Protection Profile,
[1].
The TOE also provides additional functionality, which is not covered in [1].
2.3. Package claim
This Security Target claims conformance to the assurance package EAL4 augmented with
AVA_VAN.5, ATE_DPT.2 and ALC_DVS.2. This assurance level is in line with the Security
IC Platform Protection Profile [1].
2.4. Conformance claim rationale
This TOE is equivalent to the conformance claim stated in a Security IC Platform Protection
Profile [1].
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3. Security problem definition
This chapter presents the threats, organisational security policies and assumptions for the
TOE.
The Assets, Assumptions, Threats and Organisational Security Policies are completely taken
from the Security IC Platform Protection Profile [1].
3.1. Description of Assets
Since this Security Target claims conformance to the Security IC Platform Protection Profile
[1], the assets defined in section 3.1 of the Protection Profile are applied.
3.2. Threats
This Security Target claims conformance to the Security IC Platform Protection Profile [1].
The Threats that apply to this Security Target are defined in section 3.2 of the Protection
Profile. The following table lists the threats of the Protection Profile.
Table 1 Threats defined in the Protection Profile
Threat Title
T.Leak-Inherent Inherent Information Leakage
T.Phys-Probing Physical Probing
T.Malfunction Malfunction due to Environmental Stress
T.Phys-
Manipulation
Physical Manipulation
T.Leak-Forced Forced Information Leakage
T.Abuse-Func Abuse of Functionality
T.RND Deficiency of Random Numbers
3.3. Organisational security policies
This Security Target claims conformance to the Security IC Platform Protection Profile [1].
The Organisational Security Policies that apply to this Security Target are defined in section
3.3 of the Protection Profile, they are:
P.Process-TOE Protection during TOE Development and Production
The following Organisational Security Policy is also taken from the PP [1] to facilitate the
TOE crypto services:
P.Crypto-Service Cryptographic services of the TOE
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3.4. Assumptions
This Security Target claims conformance to the Security IC Platform Protection Profile [1].
The assumptions claimed in this Security Target defined in section 3.4 of the Protection
Profile. They are specified below.
Table 2 Assumptions defined in the Protection Profile
Assumption Title
A.Process-Sec-IC Protection during Packaging, Finishing and
Personalisation
A.Resp-Appl Treatment of User Data
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4. Security objectives
This chapter provides the statement of security objectives and the security objective rationale.
For this chapter the Security IC Platform Protection Profile [1] can be applied completely.
Only a short overview is given in the following.
4.1. Security objectives for the TOE
All objectives described in the section 4.1 of the Security IC Platform Protection Profile [1]
are claimed for the TOE, these are:
Table 3 Security objectives for the TOE defined in the Protection Profile
Security Objective Title
O.Phys-
Manipulation
Protection against Physical Manipulation
O.Phys-Probing Protection against Physical Probing
O.Malfunction Protection against Malfunctions
O.Leak-Inherent Protection against Inherent Information Leakage
O.Leak-Forced Protection against Forced Information Leakage
O.Abuse-Func Protection against Abuse of Functionality
O.Identification TOE Identification
O.RND Random Numbers
The following additional security objectives are taken from the PP [1] for the provision of
hardware based Cryptographic services:
Security Objective Title
O.TDES Cryptographic service Triple-DES
O.AES Cryptographic service AES
In addition the TOE defines the following objectives:
O.RSA RSA functionality
The TOE shall provide secure cryptographic services implementing the RSA
cryptographic algorithm for encryption and decryption.
4.2. Security objectives for the security IC embedded software
All security objectives for the Security IC Embedded Software described in section 4.2 of the
Security IC Platform Protection Profile [1] are claimed for the TOE, these are:
Table 4 Security Objectives for the security IC embedded software environment defined in the Protection Profile
Security Objective Title
OE.Resp-Appl Treatment of User Data of the composite TOE
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4.3. Security objectives for the operational environment
The security objectives for the operational environment that are claimed in this Security
Target are all security objectives described in section 4.3 of the “Security IC Platform
Protection Profile” [1], which are:
Table 5 Security Objectives for the operational environment defined in the Protection Profile
Security Objective Title
OE.Process-Sec-IC Protection during composite product
manufacturing
4.4. Security objectives rationale
Section 4.4 in the Protection Profile provides a rationale how the assumptions, threats and
organisational security policies are addressed by the objectives. The table below shows this
relationship.
Assumption, Threat or
Organisational Security Policy
Security Objective
A.Resp-Appl OE.Resp-Appl
P.Process-TOE O.Identification
A.Process-Sec-IC OE.Process-Sec-IC
T.Leak-Inherent O.Leak-Inherent
T.Phys-Probing O.Phys-Probing
T.Malfunction O.Malfunction
T.Phys-Manipulation O.Phys-Manipulation
T.Leak-Forced O.Leak-Forced
T.Abuse-Func O.Abuse-Func
T.RND O.RND
For the justification of the above mapping please refer to the Protection Profile.
The table below shows how the additional organisational security policies are addressed by
objectives for the TOE.
Assumption, Threat or
Organisational Security Policy
Security Objective
P.Crypto-Service O.TDES
O.AES
O.RSA
Note that O.TDES and O.AES have been taken from the PP [1]. The others have been added.
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5. Extended Components Definitions
This Security Target uses the extended security functional requirements defined in chapter 5
of the Security IC Platform Protection Profile [1].
This Security Target does not define extended components in addition to the Protection
Profile.
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6. Security requirements
This chapter presents the statement of security requirements for the TOE and the security
requirements rationale. This chapter applies the Security IC Platform Protection Profile [1].
6.1. Definitions
In the next sections the following notation is used:
 The iteration operation is used when a component is claimed with varying operations,
it is denoted by adding “[XXX]” to the component name.
 Refinement, selection or assignment operations are used to add details or assign
specific values to components, they are indicated by italic text and explained in
footnotes.
6.2. Security Functional Requirements (SFR)
To support a better understanding of the combination Security IC Platform Protection Profile
vs. Security Target, the TOE Security Functional Requirements are presented in the following
several different sections.
6.2.1. SFRs derived from the Security IC Platform Protection Profile
The table below lists the Security Functional Requirements that are directly taken from the
Security IC Platform Protection Profile.
Security functional
requirement
Title
FRU_FLT.2 “Limited fault tolerance“
FPT_FLS.1 “Failure with preservation of secure state”
FMT_LIM.1 “Limited capabilities”
FMT_LIM.2 “Limited availability”
FAU_SAS.1 “Audit storage”
FPT_PHP.3 “Resistance to physical attack”
FDP_ITT.1 “Basic internal transfer protection”
FDP_IFC.1 “Subset information flow control”
FPT_ITT.1 “Basic internal TSF data transfer protection”
FDP_SDC.1 “Stored data confidentiality”
FDP_SDI.2 “Stored data integrity monitoring and action”
FCS_RNG.1 “Quality metric for random numbers”
Except for FAU_SAS.1, FDP_SDC.1, FDP_SDI.2 and FCS_RNG.1 all assignment and
selection operations are defined in the Protection Profile.
 In FAU_SAS.1 the left open assignment is the type of persistent memory;
 In FDP_SDC.1 the left open assignment is the memory area;
 In FDP_SDI.2 the left open assignments are the user data attributes and the action to
be taken;
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 In the FCS_RNG.1 the left open definition is the quality metric for the random
numbers.
The following statements define these completed SFRs.
FAU_SAS.1 Audit storage
Hierarchical to: No other components.
FAU_SAS.1.1 The TSF shall provide the test process before TOE Delivery1
with the
capability to store the Initialisation Data and/or Pre-personalisation
Data and/or supplements of the security IC embedded software2
in the
EEPROM3
.
Dependencies: No dependencies.
FDP_SDC.1 Stored data confidentiality
Hierarchical to: No other components.
FDP_SDC.1.1 The TSF shall ensure the confidentiality of the information of the user
data while it is stored in the EEPROM, ROM and RAM4
.
Dependencies: No dependencies.
FDP_SDI.2 Stored data integrity monitoring and action
Hierarchical to: FDP_SDI.1 Stored data integrity monitoring
FDP_SDI.2.1 The TSF shall monitor user data stored in containers controlled by the
TSF for integrity errors5
on all objects, based on the following
attributes: parity bits6
.
FDP_SDI.2.2 Upon detection of a data integrity error, the TSF shall reset7
or
interrupt8
.
Dependencies: No dependencies.
FCS_RNG.1 [PTG.2]Random number generation
Hierarchical to: No other components.
FCS_RNG.1.1[PTG.2]The TSF shall provide a physical random number generator that
Implements:
 A total failure test detects a total failure of entropy source immediately
when the RNG has started. When a total failure is detected, no random
numbers will be output.
 If a total failure of the entropy source occurs while the RNG is
being operated, the RNG prevents the output of any internal
random number that depends on some raw random numbers that
have been generated after the total failure of the entropy source 9
.
1
[assignment: list of subjects]
2
[assignment: list of audit information]
3
[assignment: type of persistent memory]
4
[assignment: memory area]
5
[assignment: integrity errors]
6
[assignment: user data attributes]
7
[assignment: action to be taken]
8
[assignment: action to be taken]
9
[selection: prevents the output of any internal random number that depends on some raw random numbers that
have been generated after the total failure of the entropy source, generates the internal random numbers with a
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 The online test shall detect non-tolerable statistical defects of the raw
random number sequence (i) immediately when the RNG has started,
and (ii) while the RNG is being operated. The TSF must not output
any random numbers before the power-up online test has finished
successfully or when a defect has been detected.
 The online test procedure shall be effective to detect non-tolerable
weaknesses of the random numbers soon.
 The online test procedure checks the quality of the raw random
number sequence. It is triggered continuously 10
. The online test is
suitable for detecting non-tolerable statistical defects of the
statistical properties of the raw random numbers within an
acceptable period of time
FCS_RNG.1.2[PTG.2]The TSF shall provide 32 bit random number words11
that meet:
 test procedure A and no other test suites12
does not distinguish the
internal random numbers from output sequences of an ideal RNG.
 The average Shannon entropy per internal random bit exceeds
0.997.
Dependencies: No dependencies.
FPT_FLS.1 Failure with preservation of secure state
Hierarchical to: No other components.
Dependencies: No dependencies.
FPT_FLS.1.1 The TSF shall preserve a secure state when the following types of
failures occur: exposure to operating conditions which may not be
tolerated according to the requirement Limited fault tolerance
(FRU_FLT.2) and where therefore a malfunction could occur13
.
Application note: The occurred failures will cause the alarm signals to be triggered,
which will result in a reset (secure state).
FPT_PHP.3 Resistance to physical attack
Hierarchical to: No other components.
Dependencies: No dependencies.
FPT_PHP.3.1 The TSF shall resist physical manipulation and physical probing14
to
the TSF15
by responding automatically such that the SFRs are always
enforced.
Application note: If a physical manipulation or physical probing attack is detected, an
alarm will be automatically triggered by the hardware, which will
cause the chip to be reset.
post-processing algorithm of class DRG.2 as long as its internal state entropy guarantees the claimed output
entropy].
10
[selection: externally, at regular intervals, continuously, applied upon specified internal events].
11
[selection: bits, octets of bits, numbers [assignment: format of the numbers]]
12
[assignment: additional standard test suites]
13
[assignment: list of types of failures in the TSF]
14
[assignment: physical tampering scenarios]
15
[assignment: list of TSF devices/elements]
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6.2.2. SFRs regarding cryptographic functionality
FCS_COP.1 [TDES] Cryptographic operation - TDES
Hierarchical to: No other components.
FCS_COP.1.1 [TDES] The TSF shall perform encryption and decryption16
in accordance
with a specified cryptographic algorithm TDES in ECB and CBC
mode17
and cryptographic key sizes of 168 bit18
that meet the
following NIST SP800-67[8], NIST SP800-38A19
[9].
Dependencies: [FDP_ITC.1 Import of user data without security attributes, or
FDP_ITC.2 Import of user data with security attributes, or
FCS_CKM.1 Cryptographic key generation]
FCS_CKM.4 Cryptographic key destruction
Application note: The TOE also supports single DES. However the security of the single
DES algorithm is not resistant against attacks with a high attack
potential. Therefore the application of single DES shall not be used in
parts of the Security Embedded Software that require high security.
FCS_COP.1 [AES] Cryptographic operation – AES
Hierarchical to: No other components.
FCS_COP.1.1 [AES] The TSF shall perform encryption and decryption20
in accordance
with a specified cryptographic algorithm AES in ECB21
and
cryptographic key sizes of 128 bit, 192 bit, 256 bit 22
that meet the
following FIPS 197[10], NIST SP800-38A23
[9].
Dependencies: [FDP_ITC.1 Import of user data without security attributes, or
FDP_ITC.2 Import of user data with security attributes, or
FCS_CKM.1 Cryptographic key generation]
FCS_CKM.4 Cryptographic key destruction
FCS_COP.1 [RSA] Cryptographic operation
Hierarchical to: No other components.
FCS_COP.1.1 [RSA] The TSF shall perform encryption and decryption24
in accordance
with a specified cryptographic algorithm Rivest, Shamir and Adleman
(RSA) in CRT and straightforward mode25
and cryptographic key
sizes from 96 bit to 2048 bit 26
(with a step size of 32 bit) that meet the
following PKCS #1 v2.1: RSA Cryptography Standard, RSA
Laboratories, June 14, 200213 27
.
Dependencies: [FDP_ITC.1 Import of user data without security attributes, or
16
[assignment: list of cryptographic operations]
17
[assignment: cryptographic algorithm]
18
[assignment: cryptographic key sizes]
19
[assignment: list of standards]
20
[assignment: list of cryptographic operations]
21
[assignment: cryptographic algorithm]
22
[assignment: cryptographic key sizes]
23
[assignment: list of standards]
24
[assignment: list of cryptographic operations]
25
[assignment: cryptographic algorithm]
26
[assignment: cryptographic key sizes]
27
[assignment: list of standards]
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FDP_ITC.2 Import of user data with security attributes, or
FCS_CKM.1 Cryptographic key generation]
FCS_CKM.4 Cryptographic key destruction
6.3. Security Assurance Requirements (SAR)
The Security Assurance Requirements claimed for the TOE are the SARs claimed in section
6.2 of the Security IC Protection Profile [1].
This Security Target will be evaluated according to Security Target evaluation (Class ASE)
The Security Assurance Requirements for the evaluation of the TOE are the components in
Assurance Evaluation level EAL4 augmented by the components ALC_DVS.2, ATE_DPT.2
and AVA_VAN.5. The table below shows the details of these assurance requirements.
Table 6 TOE assurance requirements
Security assurance
requirements
Titles
Class ADV: Development
ADV_ARC.1 Architectural design
ADV_FSP.4 Functional specification
ADV_IMP.1 Implementation representation
ADV_TDS.3 TOE design
Class AGD: Guidance documents
AGD_OPE.1 Operational user guidance
AGD_PRE.1 Preparative user guidance
Class ALC: Life-cycle support
ALC_CMC.4 CM capabilities
ALC_CMS.4 CM scope
ALC_DEL.1 Delivery
ALC_DVS.2 Development security
ALC_LCD.1 Life-cycle definition
ALC_TAT.1 Tools and techniques
Class ASE: Security Target evaluation
ASE_CCL.1 Conformance claims
ASE_ECD.1 Extended components definition
ASE_INT.1 ST introduction
ASE_OBJ.2 Security objectives
ASE_REQ.2 Derived security requirements
ASE_SPD.1 Security problem definition
ASE_TSS.1 TOE summary specification
Class ATE: Tests
ATE_COV.2 Coverage
ATE_DPT.2 Depth
ATE_FUN.1 Functional testing
ATE_IND.2 Independent testing
Class AVA: Vulnerability analysis
AVA_VAN.5 Vulnerabilty analysis
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6.4. Security requirements rationale
6.4.1. Security Functional Requirements (SFR)
The table below provides an overview of how the security functional requirements are
combined to meet the security objectives.
Security
Objectives for the
TOE
Security Functional
Requirements
Fulfilment of mapping
O.Leak-Inherent FDP_ITT.1
FPT_ITT.1
FDP_IFC.1
FDP_ITT.1 “Basic internal transfer
protection”
FPT_ITT.1 “Basic internal TSF data
transfer protection”
FDP_IFC.1 “Subset information flow
control”
O.Phys-Probing FDP_SDC.1
FPT_PHP.3
FDP_SDC.1 “Stored data confidentiality”
FPT_PHP.3 “Resistance to physical
attack”
O.Malfunction FRU_FLT.2
FPT_FLS.1
FRU_FLT.2 “Limited fault tolerance
FPT_FLS.1 “Failure with preservation of
secure state”
O.Phys-
Manipulation
FDP_SDI.2
FPT_PHP.3
FDP_SDI.2 “Stored data integrity
monitoring and action”
FPT_PHP.3 “Resistance to physical
attack”
O.Leak-Forced FDP_ITT.1
FPT_ITT.1
FDP_IFC.1
FRU_FLT.2
FPT_FLS.1
FPT_PHP.3
FDP_ITT.1 “Basic internal transfer
protection”
FPT_ITT.1 “Basic internal TSF data
transfer protection”
FDP_IFC.1 “Subset information flow
control”
FRU_FLT.2 “Limited fault tolerance
FPT_FLS.1 “Failure with preservation of
secure state”
FPT_PHP.3 “Resistance to physical
attack”
O.Abuse-Func FMT_LIM.1
FMT_LIM.2
FDP_ITT.1
FPT_ITT.1
FDP_IFC.1
FRU_FLT.2
FPT_FLS.1
FPT_PHP.3
FMT_LIM.1 “Limited capabilities”
FMT_LIM.2 “Limited availability”
FDP_ITT.1 “Basic internal transfer
protection”
FPT_ITT.1 “Basic internal TSF data
transfer protection”
FDP_IFC.1 “Subset information flow
control”
FRU_FLT.2 “Limited fault tolerance
FPT_FLS.1 “Failure with preservation of
secure state”
FPT_PHP.3 “Resistance to physical
attack”
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O.Identification FAU_SAS.1 FAU_SAS.1 “Audit storage”
O.RND FCS_RNG.1
FDP_ITT.1
FPT_ITT.1
FDP_IFC.1
FPT_PHP.3
FRU_FLT.2
FPT_FLS.1
FCS_RNG.1 “Quality metric for random
numbers”
FDP_ITT.1 “Basic internal transfer
protection”
FPT_ITT.1 “Basic internal TSF data
transfer protection”
FDP_IFC.1 “Subset information flow
control”
FPT_PHP.3 “Resistance to physical
attack”
FRU_FLT.2 “Limited fault tolerance
FPT_FLS.1 “Failure with preservation of
secure state”
O.DES FCS_COP.1
[TDES]
O.DES requires the TOE to support DES
encryption and decryption with its
specified key lengths. The claim for
FCS_COP.1 [DES] is suitable to meet the
objective O.DES.
O.RSA FCS_COP.1 [RSA] O.RSA requires the TOE to support RSA
encryption and decryption with its
specified key lengths. The claim for
FCS_COP.1 [RSA] is suitable to meet the
objective O. RSA.
O.AES FCS_COP.1 [AES] O.AES requires the TOE to support AES
encryption and decryption with its
specified key lengths. The claim for
FCS_COP.1 [AES] is suitable to meet the
objective O.AES.
OE.Process-Sec-IC
OE.Plat-Appl
OE.Resp-Appl
Security
Objectives for the
TOE
Dependencies Fulfilment of dependencies, see next
paragraph
6.4.2. Dependencies of the SFRs
The dependencies for the SFRs claimed according to the Protection Profile are all satisfied in
the set of SFRs claimed in the Protection Profile.
In the following table the dependencies of the SFRs claimed in addition to Protection Profile
is indicated.
Security
functional
requirement
Dependencies Fulfilled by security requirements in this
Security Target
FCS_COP.1
[TDES]
FDP_ITC.1 or
FDP_ITC.2 or
See explanation below this table
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FCS_CKM.1,
FCS_CKM.4
FCS_COP.1
[AES]
FDP_ITC.1 or
FDP_ITC.2 or
FCS_CKM.1,
FCS_CKM.4
See explanation below this table
FCS_COP.1
[RSA]
FDP_ITC.1 or
FDP_ITC.2 or
FCS_CKM.1,
FCS_CKM.4
See explanation below this table
The developer of the Security IC Embedded Software must ensure that the implemented
additional security functional requirements FCS_COP.1 [TDES], FCS_COP.1 [AES] and
FCS_COP.1 [RSA] are used as specified and that the User Data processed by the related
security functionality is protected as defined for the application context.
The dependent requirements for FCS_COP.1 [TDES] , FCS_COP.1 [AES] and FCS_COP.1
[RSA] address the appropriate management of cryptographic keys used by the specified
cryptographic function. All requirements concerning these management functions shall be
fulfilled by the environment (Security IC Embedded Software).
The functional requirements [FDP_ITC.1, or FDP_ITC.2 or FCS_CKM.1] and FCS_CKM.4
are not included in this Security Target since the TOE only provides a pure engine for
encryption and decryption without additional features for the handling of cryptographic keys.
Therefore the Security IC Embedded Software must fulfil these requirements related to the
needs of the realised application.
6.4.3. Security Assurance Requirements (SAR)
The SARs as defined in section 6.3 are in line with the SARs in the Security IC Platform
Protection Profile. The context of this ST is equivalent to the context described in the
Protection Profile and therefore these SARs are also applicable for this ST.
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7. TOE summary specification
This chapter provides general information to potential users of the TOE on how the TOE
implements the Security Functional Requirements in terms of “Security Functionality”.
7.1. Malfunction
Malfunctioning relates to the security functional requirements FRU_FLT.2 and FPT_FLS.1.
The TOE meets these SFRs by a group of security measures that guarantee correct operation
of the TOE.
The TOE ensures its correct operation and prevents any malfunction while the security IC
embedded software is executed by implementation of the following security features:
• Environmental detectors
monitor if environmental conditions are within the specified range
7.2. Leakage
Leakages relate to the security functional requirements FDP_ITT.1, FDP_IFC.1 and
FPT_ITT.1. The TOE meets these SFRs by implementing several measures that provide
logical protection against leakage:
• Memory encryption and bus masking
7.3. Physical manipulation and probing
Physical manipulation and probing relates to the security functional requirements
FPT_PHP.3, FDP_SDC.1 and FDP_SDI.1. The TOE meets this SFR by implementing
security measures that provides physical protection against physical probing and
manipulation.
The security measures protect the TOE against manipulation of
(i) the hardware,
(ii) the security IC embedded software in the ROM and the EEPROM,
(iii) the application data in the EEPROM and RAM including the configuration data.
It also protects User Data or TSF data against disclosure by physical probing when stored or
while being processed by the TOE.
The protection of the TOE comprises different features within the design and construction,
which make reverse-engineering and tamper attacks more difficult. The following security
measures protect the TOE against physical manipulation and probing:
• Active physical protection
Protecting hardware features by dedicated physical protection techniques.
• Data integrity checking
Verify the integrity of the data in memory during reading and writing.
• Memory encryption and bus masking
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No plain text on the bus and memory.
7.4. Abuse of functionality and Identification
Abuse of functionality and Identification relates to the security functional requirements
FMT_LIM.1, FMT_LIM.2 and FAU_SAS.1. The TOE meets these SFRs by implementation
of a test mode access control mechanism that prevents abuse of test functionality delivered as
part of the TOE.
The test functionality is not available to the user after delivery of the TOE to the Composite
Manufacturer. The TOE has implemented a hardware fuse mechanism to prevent using this
functionality after TOE delivery.
7.5. Random numbers
Random numbers relate to the security requirement FCS_RNG.1. The TOE meets this SFR by
providing a random number generator.
The random number generator fulfils the requirements of AIS31 class PTG.2[12].
On-line test circuit is implemented by hardware to check the quality of the raw random
number sequence.
7.6. Cryptographic functionality
The TOE provides the single and Triple-DES algorithm according to the NIST SP800-67[8]
and NIST SP800-38A [9] standard to meet the security requirement FCS_COP.1[TDES]. The
TOE implements the Triple-DES algorithm by means of a combination of hardware co-
processor and IC dedicated support software. It supports the DES algorithm with a single 56
bit key supporting both CBC and ECB mode. It supports the Triple-DES algorithm with three
56bit keys (168 bit) for the 3-key Triple-DES supporting both CBC and ECB mode. The keys
for the DES algorithms shall be provided by the security IC embedded software.
The TOE provides the AES algorithm according to the NIST SP800-67[8], FIPS 197[10] and
NIST SP800-38A [9] standard to meet the security requirement FCS_COP.1[AES]. The TOE
implements the AES algorithm by means of a combination of hardware co-processor and IC
dedicated support software. It supports the AES algorithm with 128 bit, 192 bit and 256 bit
key supporting ECB mode. The keys for the AES algorithms shall be provided by the security
IC embedded software.
The TOE provides the RSA algorithm according to a specified cryptographic algorithm
Rivest, Shamir and Adleman (RSA) to meet the security requirement FCS_COP.1[RSA]. It
supports the RSA algorithm with key sizes from 96 bit to 2048 bit key supporting both CRT
and straightforward mode. The keys for the RSA algorithms shall be provided by the security
IC embedded software.
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8. References
Ref Title Version Date
[1] Security IC Platform Protection Profile, BSI-CC-PP-
0084-2014
Version 1.0 13.01.2014
[2] Common Criteria for Information Technology Security
Evaluation,
Part 1: Introduction and General Model
CCMB-2012-09-001
Version 3.1
Revision 4
September
2012
[3] Common Criteria for Information Technology Security
Evaluation,
Part 2: Security Functional Requirements
CCMB-2012-09-002
Version 3.1
Revision 4
September
2012
[4] Common Criteria for Information Technology Security
Evaluation,
Part 3: Security Assurance Requirements
CCMB-2012-09-003
Version 3.1
Revision 4
September
2012
[5] Common Methodology for Information Technology
Security Evaluation (CEM), Evaluation Methodology
CCMB-2012-09-004
Version 3.1
Revision 4
September
2012
[6] NIST Special Publication 800-90A Recommendation
for Random Number Generation Using Deterministic
Random Bit Generators, January 2012
January
2012
[7] NIST DRAFT Special Publication 800-90B
Recommendation for the Entropy Sources Used for
Random Bit Generation, August 2012
August
2012
[8] NIST SP 800-67, Recommendation for the Triple Data
Encryption Algorithm (TDEA) Block Cipher, revised
January 2012, National Institute of Standards and
Technology
January
2012
[9] NIST SP 800-38A Recommendation for Block Cipher
Modes of Operation, 2001, with Addendum
Recommendation for Block Cipher Modes of
Operation: Three Variants of Ciphertext Stealing for
CBC Mode, October 2010
October
2010
[10] Federal Information Processing Standards Publication 197,
ADVANCED ENCRYPTION STANDARD (AES), U.S.
DEPARTMENT OF COMMERCE/National Institute of
Standards and Technology, November 26, 2001
November
2001
[11] Federal Information Processing Standards Publication 180-
4 SECURE HASH STANDARD U.S. DEPARTMENT OF
COMMERCE/National Institute of Standards and
Technology, 2011 February, 11
February
2011
[12] A proposal for functionality classes of random number
generators, 2011
18.09.2011